公开(公告)号：US06781890B2

公开(公告)日：2004-08-24

申请号：US10308106

申请日：2002-12-03

Applicant: Hitoshi Tanaka ,  Masanori Isoda ,  Takayuki Kawahara

Inventor： Hitoshi Tanaka ,  Masanori Isoda ,  Takayuki Kawahara

IPC: G11C700

CPC classification number: G11C16/30 ,  G11C5/145

Abstract: It is an object of the present invention to allow a voltage generating section which produces a high voltage to efficiently produce a high voltage, and to reduce a layout area of a semiconductor chip. An intermediate voltage charge pump circuit is provided in a voltage producing section of a flash memory. The intermediate voltage charge pump circuit comprises switching elements, a first charge pump circuit comprising capacitors, a second charge pump circuit comprising switching elements, capacitors and an equalizer comprising switching elements. These elements are driven by driving signals. A period during which all of one contacts of parasitic capacities Capacitor are brought into floating state temporarily is formed. After corresponding parasitic capacities are short-circuited by the switching elements, nodes thereof are electrically charged or discharged, and a high voltage is produced while reusing electric charge while using electric charge discharged to a reference potential by next cycle.

Abstract translation: 本发明的目的是允许产生高电压的电压产生部分有效地产生高电压并且减小半导体芯片的布局面积。 中间电压电荷泵电路设置在闪速存储器的电压产生部分中。 中间电压电荷泵电路包括开关元件，包括电容器的第一电荷泵电路，包括开关元件的第二电荷泵电路，电容器和包括开关元件的均衡器。 这些元件由驱动信号驱动。 形成寄生电容电容器的一个触点暂时进入浮置状态的期间。 在相应的寄生电容被开关元件短路之后，其节点被充电或放电，并且在再次使用电荷的同时产生高电压，同时使用在下一个周期中放电到参考电位的电荷。

公开(公告)号：US06749349B2

公开(公告)日：2004-06-15

申请号：US10187994

申请日：2002-07-03

Applicant: Hitoshi Tanaka

Inventor： Hitoshi Tanaka

IPC: G03B908

CPC classification number: G03B9/08

Abstract: A sector blade driving device includes a plurality of sector blades which define an adjustable photographic aperture, and a cylindrical member which surrounds the periphery of the sector blades to prevent harmful light from entering the photographic aperture from outside of the sector blade driving device. At least part of the cylindrical member which the sector blades press against when the plurality of sector blades are fully opened is made of a resilient material.

Abstract translation: 扇形叶片驱动装置包括限定可调节的照相孔的多个扇形叶片和围绕扇形叶片的周边的圆柱形构件，以防止有害光从扇形叶片驱动装置的外部进入摄影孔。 当多个扇形叶片完全打开时扇形叶片压紧的圆柱形构件的至少一部分由弹性材料制成。

公开(公告)号：US06703891B2

公开(公告)日：2004-03-09

申请号：US10179222

申请日：2002-06-26

Applicant: Hitoshi Tanaka

Inventor： Hitoshi Tanaka

IPC: G05F302

CPC classification number: G11C11/4074 ,  G11C5/145 ,  H02M3/073 ,  H02M2003/077

Abstract: A semiconductor integrated circuit device having an internal voltage generating circuit which generates a voltage two or more times higher than an operating voltage while at the same time reducing the voltage applied to a device, thereby ensuring the device reliability. In a charge pump circuit driven by supply voltage VDD, a maximum of 2VDD or a similar level voltage is applied between the drain and source of a MOSFET, the MOSFET being connected in series with a conduction MOSFET of the same type, the gate of which is supplied with VD−VDD, or a potential which is VDD lower than VD, the drain potential before its connection. The gate potential is obtained directly from a node in said charge pump which generates a voltage pulse synchronized with the voltage between the drain and source of that MOSFET, or through another rectifier device branched via a capacitor from the node.

Abstract translation: 一种具有内部电压产生电路的半导体集成电路器件，其产生比工作电压高两倍或更多倍的电压，同时降低施加到器件的电压，从而确保器件的可靠性。 在由电源电压VDD驱动的电荷泵电路中，在MOSFET的漏极和源极之间施加最大2VDD或类似的电平电压，MOSFET与相同类型的导通MOSFET串联，其栅极 VD-VDD供电，或VDD低于VD的电位，连接前的漏极电位。 栅极电位直接从所述电荷泵中的节点获得，其产生与该MOSFET的漏极和源极之间的电压同步的电压脉冲，或通过经由电容器从该节点分支的另一个整流器件。

公开(公告)号：US06599660B2

公开(公告)日：2003-07-29

申请号：US09799627

申请日：2001-03-07

Applicant: Takashi Oda ,  Hideki Okajima ,  Yukichi Uesugi ,  Hitoshi Tanaka ,  Yoshinobu Okumura

Inventor： Takashi Oda ,  Hideki Okajima ,  Yukichi Uesugi ,  Hitoshi Tanaka ,  Yoshinobu Okumura

IPC: H01M642

CPC classification number: H01M2/202 ,  H01M2/022 ,  Y10T29/49114

Abstract: A battery module of the present invention comprises an annular connecting member 10 having an aperture 14 at a position corresponding to a cap 8 provided on a sealing plate 7 and between the sealing member 7 of one cell B and a bottom of a can 6 of the other cell A. The annular connecting member 10 comprises an annular base portion 11 having its outer diameter smaller than an inner diameter of the opening portion of the can 6, a convex portion 12 with bottom protruding upward or downward alternately from the annular base portion 11, and a projection 13 projecting from the bottom of the convex portion 12. Thereby, the connecting portion between the cell A and the cell B has a collecting path of a length between both projections 13, namely, a length between the sealing plate 7 of the cell B and the bottom of the can 6 of the cell A, whereby the voltage drop across the connecting portion decreases, resulting in a battery module having high operation voltage.

Abstract translation: 本发明的电池模块包括环形连接构件10，该环形连接构件10在对应于设置在密封板7上的帽8的位置和一个单元B的密封构件7和罐6的底部之间的位置处具有孔14 环形连接构件10包括其外径小于罐6的开口部分的内径的环形基部11，具有从环形基部11交替地向上或向下突出的底部的凸部12 以及从凸部12的底部突出的突起13.由此，电池A和电池B之间的连接部分具有在两个突起13之间的长度的收集路径，即，两个突起13的密封板7之间的长度 电池B和电池A的罐6的底部，由此连接部分两端的电压降降低，导致电池模块具有高的工作电压。

公开(公告)号：US06535435B2

公开(公告)日：2003-03-18

申请号：US10012522

申请日：2001-12-12

Applicant: Hitoshi Tanaka ,  Masakazu Aoki ,  Shinichiro Kimura ,  Hiromasa Noda ,  Tomonori Sekiguchi

Inventor： Hitoshi Tanaka ,  Masakazu Aoki ,  Shinichiro Kimura ,  Hiromasa Noda ,  Tomonori Sekiguchi

IPC: G11C700

CPC classification number: H01L27/0222 ,  G11C5/145 ,  G11C5/147 ,  G11C11/4074 ,  H01L27/10897

Abstract: A reference voltage generation circuit is provided which includes a p-channel type MOSFET used as an input transistor to allow a sufficient current to flow through a differential amplifier even if the threshold voltages of MOSFETs used in the differential amplifier significantly increase. A push-pull conversion circuit is coupled to the differential amplifier and has a double end configuration to provide a sufficiently high level to drive a p-channel output buffer. This arrangement allows a stable operation at a sufficiently low power supply voltage even if the threshold voltages of the MOSFETs forming the differential amplifier are high. It also allows quick activation when the power is turned on and provides high stability.

Abstract translation: 提供了一种参考电压产生电路，其包括用作输入晶体管的p沟道型MOSFET，以允许足够的电流流过差分放大器，即使差分放大器中使用的MOSFET的阈值电压显着增加。 推挽转换电路耦合到差分放大器并且具有双端配置以提供足够高的电平来驱动p沟道输出缓冲器。 即使形成差分放大器的MOSFET的阈值电压高，这种布置允许在足够低的电源电压下的稳定操作。 它还允许在电源打开时快速启动并提供高稳定性。

公开(公告)号：US06359184B1

公开(公告)日：2002-03-19

申请号：US09487538

申请日：2000-01-19

Applicant: Hajime Kato ,  Hitoshi Tanaka ,  Kazuyoshi Iwayama ,  Ryoji Ichioka

Inventor： Hajime Kato ,  Hitoshi Tanaka ,  Kazuyoshi Iwayama ,  Ryoji Ichioka

IPC: C07C600

CPC classification number: B01J29/26 ,  B01J29/20 ,  C07C6/126 ,  C07C2521/04 ,  C07C2521/06 ,  C07C2521/08 ,  C07C2521/10 ,  C07C2521/12 ,  C07C2521/16 ,  C07C2529/18 ,  C07C2529/22 ,  C07C2529/24 ,  C07C2529/26 ,  Y02P20/52

Abstract: Disclosed herein is a catalyst composition for transalkylation of alkylaromatic hydrocarbons which exhibits the percent conversion of ethyltoluene higher than 50 wt %, is composed of mordenite (100 pbw), inorganic oxide and/or clay (25-150 pbw), and at least one metal component of rhenium, platinum, and nickel, and contains mordenite such that the maximum diameter of secondary particles of mordenite is smaller than 10 &mgr;m. Disclosed also herein is a process for producing xylene by the aid of said catalyst from alkylaromatic hydrocarbons containing C9 alkylaromatic hydrocarbons containing more than 5 wt % ethyltoluene and less than 0.5 wt % naphthalene, in the presence of hydrogen.

Abstract translation: 本文公开了烷基芳族烃的烷基转移催化剂组合物，其表现出高于50重量％的乙基甲苯的转化百分比，由丝光沸石（100pbw），无机氧化物和/或粘土（25-150pbw）组成，并且至少一个 铼，铂和镍的金属成分，并含有丝光沸石，使得丝光沸石的二次粒子的最大直径小于10μm。 本文还公开了在氢气存在下，借助于所述催化剂从含有大于5重量％乙基甲苯和小于0.5重量％萘的C 9烷基芳族烃的烷基芳烃生产二甲苯的方法。

公开(公告)号：US06339344B1

公开(公告)日：2002-01-15

申请号：US09497280

申请日：2000-02-02

Applicant: Takeshi Sakata ,  Hitoshi Tanaka ,  Osamu Nagashima ,  Masafumi Ohi ,  Sadayuki Morita

Inventor： Takeshi Sakata ,  Hitoshi Tanaka ,  Osamu Nagashima ,  Masafumi Ohi ,  Sadayuki Morita

IPC: H03K190175

CPC classification number: H03K19/018528

Abstract: Differential amplifier circuits that receive input signals fed through external terminals are served with a first operation voltage and a second operation voltage through a first switching MOSFET and a second switching MOSFET, said first and second switching MOSFETs are turned on by a bias voltage-generating circuit when said input signal is near a central voltage of said first and second operation voltages, control voltages are formed to turn either said first switching MOSFET or said second switching MOSFET on and to turn the other one off to produce a corresponding output signal when the input signal continuously assumes said first voltage or said second voltage for a predetermined period of time, thereby to supply an input signal of a first amplitude corresponding to said first operation voltage and said second operation voltage as well as an input signal of a second amplitude corresponding to a predetermined intermediate voltage between said first operation voltage and said second operation voltage.

Abstract translation: 接收通过外部端子馈送的输入信号的差分放大器电路通过第一开关MOSFET和第二开关MOSFET被提供第一工作电压和第二工作电压，所述第一和第二开关MOSFET由偏置电压产生电路 当所述输入信号接近所述第一和第二操作电压的中心电压时，形成控制电压以使所述第一开关MOSFET或所述第二开关MOSFET导通，并将另一个断开以产生相应的输出信号，当输入 信号连续地采取所述第一电压或所述第二电压预定的时间段，从而提供对应于所述第一操作电压和所述第二操作电压的第一幅度的输入信号以及对应于所述第一操作电压的第二幅度的输入信号 所述第一操作电压和所述第二操作电压之间的预定中间电压 工作电压。

公开(公告)号：US06335898B2

公开(公告)日：2002-01-01

申请号：US09808943

申请日：2001-03-16

Applicant: Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

Inventor： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

IPC: G11C800

CPC classification number: G11C7/02 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/1072 ,  H01L27/10897

Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.

公开(公告)号：US06335301B1

公开(公告)日：2002-01-01

申请号：US09526888

申请日：2000-03-16

Applicant: Tatuya Kikuchi ,  Hitoshi Tanaka

Inventor： Tatuya Kikuchi ,  Hitoshi Tanaka

IPC: C04B3546

CPC classification number: H01G4/1245 ,  C04B35/49

Abstract: A dielectric ceramic composition, comprised of a main component expressed by a composition formula [SrZrO3]x+[CaTiO3](1−x) wherein the “x” satisfies 1.00≧x≧0.60, and sub components such as B2O3, SiO2, ZnO, Al2O3 and Li2O. Where the amounts of B2O3, SiO2, ZnO, Al2O3 and Li2O respectively equal “a”, “b”, “c”, “d”, and “e” parts by weight with respect to 100 parts by weight of the main component, 1.80>a≧0.25, 1.80>b≧0.20, 1.80>c≧0, 1.10>d≧0, 6.30>e≧0.05 and 10.00>a+b+c+d+e≧0.50 are satisfied. The dielectric ceramic composition can be burned at 1000° C. or less and is able to be used in a multi-layer chip capacitor suitable for high frequencies capable of using Cu or Ag as an internal conductor.

Abstract translation: 一种介电陶瓷组合物，其中由“x”满足1.00> = x> = 0.60的组成式[SrZrO3] x + [CaTiO3]（1-x）表示的主要成分，以及诸如B 2 O 3，SiO 2， ZnO，Al2O3和Li2O。 当相对于100重量份的主要成分，B 2 O 3，SiO 2，ZnO，Al 2 O 3和Li 2 O的量分别等于“a”，“b”，“c”，“d”和“e” 1.80> a> = 0.25,1.80> b> = 0.20,1.80> c> = 0,1.10> d> = 0,6.30> e> = 0.05和10.00> a + b + c + d + e> = 0.50 满意。 电介质陶瓷组合物可以在1000℃以下燃烧，并且能够用于适用于能够使用Cu或Ag作为内部导体的高频的多层片式电容器。

公开(公告)号：US06314044B1

公开(公告)日：2001-11-06

申请号：US09594840

申请日：2000-06-15

Applicant: Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

Inventor： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

IPC: G11C800

CPC classification number: G11C8/12

Abstract: A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or −1 arithmetic operation are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

Abstract translation: 安装成与逻辑电路混合的RAM具有多个存储器垫和为多个存储器垫提供的一个控制电路。 分别提供用于分别执行+1或-1运算的算术电路，以对应于相应的存储器垫并且以级联形式电连接。 初始级算术电路的输入端被提供地址设定固定地址信号。 提供给下一个和后续运算电路的输入信号或从其输出的信号被定义为自己分配的地址信号（分配给相应的存储器垫的那些）。 与上述每个运算电路相关联地提供的比较器比较了存储器访问时输入的地址信号和地址信号之间的一致性。 基于所得到的一致信号来选择相应的存储器垫。