利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

179 条记录 (耗时 0.027 秒)

    Reference voltage generator permitting stable operation
    1.
    发明授权
    Reference voltage generator permitting stable operation 有权
    参考电压发生器允许稳定运行

    公开(公告)号：US06535435B2

    公开(公告)日：2003-03-18

    申请号：US10012522

    申请日：2001-12-12

    申请人： Hitoshi Tanaka ,  Masakazu Aoki ,  Shinichiro Kimura ,  Hiromasa Noda ,  Tomonori Sekiguchi

    发明人： Hitoshi Tanaka ,  Masakazu Aoki ,  Shinichiro Kimura ,  Hiromasa Noda ,  Tomonori Sekiguchi

    IPC分类号： G11C700

    CPC分类号： H01L27/0222 ,  G11C5/145 ,  G11C5/147 ,  G11C11/4074 ,  H01L27/10897

    摘要： A reference voltage generation circuit is provided which includes a p-channel type MOSFET used as an input transistor to allow a sufficient current to flow through a differential amplifier even if the threshold voltages of MOSFETs used in the differential amplifier significantly increase. A push-pull conversion circuit is coupled to the differential amplifier and has a double end configuration to provide a sufficiently high level to drive a p-channel output buffer. This arrangement allows a stable operation at a sufficiently low power supply voltage even if the threshold voltages of the MOSFETs forming the differential amplifier are high. It also allows quick activation when the power is turned on and provides high stability.

    摘要翻译： 提供了一种参考电压产生电路，其包括用作输入晶体管的p沟道型MOSFET，以允许足够的电流流过差分放大器，即使差分放大器中使用的MOSFET的阈值电压显着增加。 推挽转换电路耦合到差分放大器并且具有双端配置以提供足够高的电平来驱动p沟道输出缓冲器。 即使形成差分放大器的MOSFET的阈值电压高，这种布置允许在足够低的电源电压下的稳定操作。 它还允许在电源打开时快速启动并提供高稳定性。

    Semiconductor integrated circuit device
    2.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US06335893B1

    公开(公告)日：2002-01-01

    申请号：US09446025

    申请日：1999-12-16

    申请人： Hitoshi Tanaka ,  Masakazu Aoki ,  Shinichiro Kimura ,  Hiromasa Noda ,  Tomonori Sekiguchi

    发明人： Hitoshi Tanaka ,  Masakazu Aoki ,  Shinichiro Kimura ,  Hiromasa Noda ,  Tomonori Sekiguchi

    IPC分类号： G11C700

    CPC分类号： H01L27/0222 ,  G11C5/145 ,  G11C5/147 ,  G11C11/4074 ,  H01L27/10897

    摘要： In a semiconductor integrated circuit device having a first circuit block operating on a power supply voltage supplied through an external terminal and a second circuit block operating on an internal voltage generated by a power supply circuit, a voltage having an absolute value greater than that of the internal voltage is generated by a charge pump circuit; variable impedance means is provided between the output voltage and the internal voltage; and a reference voltage and the internal voltage are compared by a differential amplifier circuit operating on the output voltage generated by the charge pump circuit and the variable impedance means is controlled such that those voltages agree with each other.

    摘要翻译： 在具有通过外部端子提供的电源电压工作的第一电路块和对由电源电路产生的内部电压进行工作的第二电路块的半导体集成电路装置中，绝对值大于 内部电压由电荷泵电路产生; 可变阻抗装置设置在输出电压和内部电压之间; 并且通过对由电荷泵电路产生的输出电压进行操作的差分放大器电路来比较内部电压，并且控制可变阻抗装置使得这些电压彼此一致。

    Sense amplifier for semiconductor memory device
    3.
    发明申请
    Sense amplifier for semiconductor memory device 有权
    用于半导体存储器件的检测放大器

    公开(公告)号：US20070147152A1

    公开(公告)日：2007-06-28

    申请号：US11706409

    申请日：2007-02-15

    申请人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

    发明人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

    IPC分类号： G11C7/02

    CPC分类号： G11C7/062 ,  G11C5/063 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C29/1201 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10897

    摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

    摘要翻译： 本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。 由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。 此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。 此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。

    Semiconductor memory
    4.
    发明申请
    Semiconductor memory 有权
    半导体存储器

    公开(公告)号：US20060034133A1

    公开(公告)日：2006-02-16

    申请号：US10534049

    申请日：2002-11-08

    申请人： Tomonori Sekiguchi ,  Shinichi Myatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

    发明人： Tomonori Sekiguchi ,  Shinichi Myatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

    IPC分类号： G11C7/00

    CPC分类号： G11C7/062 ,  G11C5/063 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C29/1201 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10897

    摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

    摘要翻译： 本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。 由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。 此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。 此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06882557B2

    公开(公告)日：2005-04-19

    申请号：US10656351

    申请日：2003-09-05

    申请人： Kazuhiko Kajigaya ,  Hiromasa Noda ,  Shinichi Miyatake ,  Riichiro Takemura ,  Tomonori Sekiguchi ,  Takeshi Sakata

    发明人： Kazuhiko Kajigaya ,  Hiromasa Noda ,  Shinichi Miyatake ,  Riichiro Takemura ,  Tomonori Sekiguchi ,  Takeshi Sakata

    IPC分类号： H01L21/8242 ,  G11C5/06 ,  G11C7/18 ,  G11C11/22 ,  G11C11/401 ,  G11C11/4097 ,  G11C29/50 ,  H01L27/02 ,  H01L27/108

    CPC分类号： G11C29/50 ,  G11C7/18 ,  G11C11/4097 ,  G11C2207/005 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/10897

    摘要： The contact resistance of each switch is reduced, and the on-resistances of all of the switches are set to be uniform, while the area required for arrangement of bit line selection switches is not increased.The switches are connected to one-side ends of the bit lines provided at the odd-numbered positions, and are connected to the other-side ends of the bit lines provided at the even-numbered positions. A pair of odd-numbered or even-numbered bit lines are connected to the terminals of each sense amplifier, respectively. The memory cells are arranged at predetermined intersection points of the word lies and the bit lines, the number of the predetermined intersection points being equal to half of all the intersection points thereof, in such a manner that when one word line is selected, the memory cells connected to the selected word-line can be electrically connected in such a manner that one memory cell is electrically connected to each terminal of the unit circuits.

    摘要翻译： 每个开关的接触电阻减小，并且所有开关的导通电阻被设置为均匀，而位线选择开关的布置所需的面积不增加。 开关连接到设置在奇数位置的位线的一侧端子，并连接到设置在偶数位置的位线的另一端。 一对奇数或偶数位线分别连接到每个读出放大器的端子。 存储单元被布置在字位置和位线的预定交点处，预定交点的数量等于其所有交点的一半，使得当选择一个字线时，存储器 连接到所选字线的单元可以以一个存储单元电连接到单元电路的每个端子的方式电连接。

    Sense amplifier for semiconductor memory device
    8.
    发明申请
    Sense amplifier for semiconductor memory device 有权
    用于半导体存储器件的检测放大器

    公开(公告)号：US20090059702A1

    公开(公告)日：2009-03-05

    申请号：US12285527

    申请日：2008-10-08

    申请人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

    发明人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

    IPC分类号： G11C7/06

    CPC分类号： G11C7/062 ,  G11C5/063 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C29/1201 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10897

    摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

    摘要翻译： 本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。 由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。 此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。 此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。

    Sense amplifier for semiconductor memory device
    9.
    发明授权
    Sense amplifier for semiconductor memory device 有权
    用于半导体存储器件的检测放大器

    公开(公告)号：US07447091B2

    公开(公告)日：2008-11-04

    申请号：US11706409

    申请日：2007-02-15

    申请人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

    发明人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

    IPC分类号： G11C7/02

    CPC分类号： G11C7/062 ,  G11C5/063 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C29/1201 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10897

    摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

    摘要翻译： 本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。 由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。 此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。 此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。