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    Cuckoo filters and cuckoo hash tables with biasing, compression, and decoupled logical sparsity
    243.
    发明授权
    Cuckoo filters and cuckoo hash tables with biasing, compression, and decoupled logical sparsity 有权

    公开(公告)号：US11762828B2

    公开(公告)日：2023-09-19

    申请号：US16104662

    申请日：2018-08-17

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alexander D. Breslow ,  Nuwan S. Jayasena

    IPC: G06F16/00 ,  G06F16/22

    CPC classification number: G06F16/2255

    Abstract: A method includes, for each key of a plurality of keys, identifying from a set of buckets a first bucket for the key based on a first hash function, and identifying from the set of buckets a second bucket for the key based on a second hash function. An entry for the key is stored in a bucket selected from one of the first bucket and the second bucket. The entry is inserted in a sequence of entries in a memory block. A position of the entry in the sequence of entries corresponds to the selected bucket. For each bucket in the set of buckets, an indication of a number of entries in the bucket is recorded.

    Matrix multiplication unit with flexible precision operations
    244.
    发明授权
    Matrix multiplication unit with flexible precision operations 有权

    公开(公告)号：US11762658B2

    公开(公告)日：2023-09-19

    申请号：US16581252

    申请日：2019-09-24

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Bin He ,  Michael Mantor ,  Jiasheng Chen ,  Jian Huang

    IPC: G06F9/30 ,  G06F17/16 ,  G06F9/38 ,  G06F9/54

    CPC classification number: G06F9/30036 ,  G06F9/30101 ,  G06F9/3877 ,  G06F9/544 ,  G06F17/16

    Abstract: A processing unit such as a graphics processing unit (GPU) includes a plurality of vector signal processors (VSPs) that include multiply/accumulate elements. The processing unit also includes a plurality of registers associated with the plurality of VSPs. First portions of first and second matrices are fetched into the plurality of registers prior to a first round that includes a plurality of iterations. The multiply/accumulate elements perform matrix multiplication and accumulation on different combinations of subsets of the first portions of the first and second matrices in the plurality of iterations prior to fetching second portions of the first and second matrices into the plurality of registers for a second round. The accumulated results of multiplying the first portions of the first and second matrices are written into an output buffer in response to completing the plurality of iterations.

    Performing scan data transfer inside multi-die package with SERDES functionality
    245.
    发明授权
    Performing scan data transfer inside multi-die package with SERDES functionality 有权

    公开(公告)号：US11762017B2

    公开(公告)日：2023-09-19

    申请号：US17532469

    申请日：2021-11-22

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Ahmet Tokuz ,  Saurabh Upadhyay

    IPC: G01R31/3185 ,  G01R31/3177 ,  G06F11/22

    CPC classification number: G01R31/318583 ,  G01R31/3177 ,  G01R31/318572 ,  G06F11/2236

    Abstract: A system for performing a scan test of a processor core includes a scan test module and a processor including a processor core and an input/output die, where the input/output die is coupled to the processor core. The scan test module transmits, in parallel to the input/output die, scan test input data. A serializer/deserializer module of the input/output die receives the input data, serializes the input data, and transmits the serialized input data to the processor core. A serializer/deserializer module of the processor core receives the serialized scan test input data, deserializes the input data, receives result data generated in dependence upon the input data, serializes the result data, and transmits the serialized result data to the input/output die. The input/output die serializer/deserializer module receives the result data, deserializes the result data, and provides the result data to the scan test module. Error detection can be carried out through redundancy.

    VERTICAL AND HORIZONTAL BROADCAST OF SHARED OPERANDS
    247.
    发明公开
    VERTICAL AND HORIZONTAL BROADCAST OF SHARED OPERANDS 审中-公开

    公开(公告)号：US20230289191A1

    公开(公告)日：2023-09-14

    申请号：US18128642

    申请日：2023-03-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Sateesh LAGUDU ,  Allen H. Rush ,  Michael Mantor ,  Arun Vaidyanathan Ananthanarayan ,  Prasad Nagabhushanamgari ,  Maxim V. Kazakov

    IPC: G06F9/38 ,  G06F13/28 ,  G06F13/40

    CPC classification number: G06F9/3887 ,  G06F13/28 ,  G06F13/4027

    Abstract: An array processor includes processor element arrays distributed in rows and columns. The processor element arrays perform operations on parameter values. The array processor also includes memory interfaces that broadcast sets of the parameter values to mutually exclusive subsets of the rows and columns of the processor element arrays. In some cases, the array processor includes single-instruction-multiple-data (SIMD) units including subsets of the processor element arrays in corresponding rows, workgroup processors (WGPs) including subsets of the SIMD units, and a memory fabric configured to interconnect with an external memory that stores the parameter values. The memory interfaces broadcast the parameter values to the SIMD units that include the processor element arrays in rows associated with the memory interfaces and columns of processor element arrays that are implemented across the SIMD units in the WGPs. The memory interfaces access the parameter values from the external memory via the memory fabric.

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