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    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    241.
    发明申请
    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20090227091A1

    公开(公告)日：2009-09-10

    申请号：US12158988

    申请日：2006-12-18

    Applicant: Jan Sonsky ,  Wibo D. Van Noort

    Inventor： Jan Sonsky ,  Wibo D. Van Noort

    IPC: H01L21/20

    CPC classification number: H01L21/76229 ,  B81C1/00158 ,  B81C2201/014

    Abstract: A method of manufacturing a semiconductor device wherein a laminate structure comprising a sacrificial layer is sandwiched between two etch stop layers (8,11) and which separates a semiconductor membrane (9) from a bulk substrate (1) is used to provide an underetched structure. Access trenches (4) and support trenches (5) are formed in the layered structure through the thickness of the semiconductor layer (9) and through the upper etch stop layer (8). The support trenches extend deeper through the sacrificial layer (12) and the lower etch stop layer and are filled. The sacrificial layer is exposed and etched away selectively to the etch stop layers to form a cavity (30) and realise a semiconductor membrane which is attached to the bulk substrate via a vertical support structure comprising the filled support trenches.

    Abstract translation: 一种制造半导体器件的方法，其中包括牺牲层的层压结构被夹在两个蚀刻停止层（8,11）之间，并且将半导体膜（9）与体基板（1）分离，以提供未刻划的结构 。 通过半导体层（9）的厚度和通过上蚀刻停止层（8）在层状结构中形成通路沟槽（4）和支撑沟槽（5）。 支撑沟槽通过牺牲层（12）和下蚀刻停止层更深地延伸并被填充。 牺牲层被暴露并被选择性地蚀刻到蚀刻停止层以形成空腔（30）并且实现通过包括填充的支撑沟槽的垂直支撑结构附接到主体衬底的半导体膜。

    MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS) DEVICE
    242.
    发明申请
    MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS) DEVICE 有权
    微电子机械系统（MEMS）器件

    公开(公告)号：US20090179233A1

    公开(公告)日：2009-07-16

    申请号：US12014810

    申请日：2008-01-16

    Applicant: Chien-Hsing Lee ,  Tsung-Min Hsieh

    Inventor： Chien-Hsing Lee ,  Tsung-Min Hsieh

    IPC: H01L21/50 ,  H01L29/66

    CPC classification number: B81C1/00246 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0257 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0735

    Abstract: The present invention provides a MEMS device, be implemented on many MEMS device, such as MEMS microphone, MEMS speaker, MEMS accelerometer, MEMS gyroscope. The MEMS device includes a substrate. A dielectric structural layer is disposed over the substrate, wherein the dielectric structural layer has an opening to expose the substrate. A diaphragm layer is disposed over the dielectric structural layer, wherein the diaphragm layer covers the opening of the dielectric structural layer to form a chamber. A conductive electrode structure is adapted in the diaphragm layer and the substrate to store nonvolatile charges.

    Abstract translation: 本发明提供了一种MEMS器件，可在许多MEMS器件上实现，例如MEMS麦克风，MEMS扬声器，MEMS加速度计，MEMS陀螺仪。 MEMS器件包括衬底。 电介质结构层设置在衬底上，其中电介质结构层具有露出衬底的开口。 隔膜层设置在电介质结构层上，其中隔膜层覆盖电介质结构层的开口以形成室。 导电电极结构适用于隔膜层和基板以存储非易失性电荷。

    SILICON-RICH SILICON NITRIDES AS ETCH STOP IN MEMS MANUFACTURE
    244.
    发明申请
    SILICON-RICH SILICON NITRIDES AS ETCH STOP IN MEMS MANUFACTURE 失效
    有机硅制成的硅氧化物作为MEMS制造中的停止

    公开(公告)号：US20080226929A1

    公开(公告)日：2008-09-18

    申请号：US12128469

    申请日：2008-05-28

    Applicant: Wonsuk Chung ,  Steve Zee ,  Teruo Sasagawa

    Inventor： Wonsuk Chung ,  Steve Zee ,  Teruo Sasagawa

    IPC: B32B15/04

    CPC classification number: B81C1/00801 ,  B81B2201/047 ,  B81C2201/014 ,  G02B26/001 ,  Y10T428/31678

    Abstract: The fabrication of a MEMS device such as an interferometric modulator is improved by employing an etch stop layer between a sacrificial layer and a an electrode. The etch stop may reduce undesirable over-etching of the sacrificial layer and the electrode. The etch stop layer may also serve as a barrier layer, buffer layer, and/or template layer. The etch stop layer may include silicon-rich silicon nitride.

    Abstract translation: 通过在牺牲层和电极之间采用蚀刻停止层来改善诸如干涉式调制器之类的MEMS器件的制造。 蚀刻停止可以减少对牺牲层和电极的不希望的过蚀刻。 蚀刻停止层也可以用作阻挡层，缓冲层和/或模板层。 蚀刻停止层可以包括富硅的氮化硅。

    Method for fabricating vertical offset structure
    245.
    发明授权
    Method for fabricating vertical offset structure 失效
    垂直偏移结构的制作方法

    公开(公告)号：US07214559B2

    公开(公告)日：2007-05-08

    申请号：US11134521

    申请日：2005-05-23

    Applicant: Jong-pal Kim ,  Sang-woo Lee ,  Byeung-leul Lee

    Inventor： Jong-pal Kim ,  Sang-woo Lee ,  Byeung-leul Lee

    IPC: H01L21/00

    CPC classification number: B81C1/00626 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/045 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81C2201/014 ,  G01P15/0802 ,  G01P15/125 ,  G02B26/0841

    Abstract: A method for fabricating a vertical offset structure that forms a complete vertical offset on a wafer includes a first trench forming step of forming first trenches on a wafer; a first etching step of performing a first patterning for determining etching positions of second and third trenches by depositing a first thin film on the wafer, performing a second patterning for temporarily protecting the etching position of the third trench by depositing a second thin film on the first thin film and the wafer, and then forming the second trenches by etching the wafer; a second etching step of forming a protection layer on side surfaces of the second trenches and then vertically extending the second trenches by etching the wafer; a third etching step of removing the second thin film and then forming the third trench by etching a position from which the second thin film is removed; and a fourth etching step of horizontally extending the second trenches vertically extended at the second etching step and the third trench by etching the wafer.

    Abstract translation: 用于制造在晶片上形成完整的垂直偏移的垂直偏移结构的方法包括在晶片上形成第一沟槽的第一沟槽形成步骤; 第一蚀刻步骤，通过在晶片上沉积第一薄膜来执行用于确定第二和第三沟槽的蚀刻位置的第一图案化，执行用于暂时保护第三沟槽的蚀刻位置的第二图案化， 第一薄膜和晶片，然后通过蚀刻晶片形成第二沟槽; 第二蚀刻步骤，在所述第二沟槽的侧表面上形成保护层，然后通过蚀刻所述晶片垂直延伸所述第二沟槽; 第三蚀刻步骤，通过蚀刻除去第二薄膜的位置来去除第二薄膜，然后形成第三沟槽; 以及第四蚀刻步骤，通过蚀刻晶片水平延伸在第二蚀刻步骤和第三沟槽处垂直延伸的第二沟槽。

    Process for fabricating monolithic membrane substrate structures with well-controlled air gaps
    246.
    发明申请
    Process for fabricating monolithic membrane substrate structures with well-controlled air gaps 审中-公开
    制造具有良好控制气隙的单片膜基片结构的方法

    公开(公告)号：US20060196843A1

    公开(公告)日：2006-09-07

    申请号：US11416529

    申请日：2006-05-02

    Applicant: Sarabjit Mehta

    Inventor： Sarabjit Mehta

    IPC: C23F1/00 ,  B44C1/22 ,  H01L21/00

    CPC classification number: B81C1/00158 ,  B81C2201/014 ,  Y10T428/24479 ,  Y10T428/2462

    Abstract: A process for fabricating monolithic membrane structures having air gaps is disclosed, comprising the steps of: providing a wafer; depositing and patterning a protective layer on the wafer; providing a trench in the wafer; depositing and patterning a metal in the trench; depositing and patterning a sacrificial layer on the metal; depositing and patterning a membrane pad on the sacrificial layer; providing a polymeric film on the protective layer and sacrificial layer, wherein part of the polymeric film has a tensile stress; and releasing part of the polymeric film from the protective layer and sacrificial layer, wherein the tensile stress of a portion of the polymeric film releases the portion of the polymeric film from the wafer and generates the air gap.

    Abstract translation: 公开了一种用于制造具有气隙的整体膜结构的方法，包括以下步骤：提供晶片; 在晶片上沉积和图案化保护层; 在晶片中提供沟槽; 在沟槽中沉积和图案化金属; 在金属上沉积和图案化牺牲层; 在牺牲层上沉积和图案化膜垫; 在保护层和牺牲层上提供聚合物膜，其中聚合物膜的一部分具有拉伸应力; 以及从所述保护层和牺牲层释放所述聚合物膜的一部分，其中所述聚合物膜的一部分的拉伸应力从所述晶片释放所述聚合物膜的所述部分并产生所述气隙。

    Method for manufacturing microstructure
    250.
    发明授权
    Method for manufacturing microstructure 有权
    微结构制造方法

    公开(公告)号：US07033515B2

    公开(公告)日：2006-04-25

    申请号：US10686764

    申请日：2003-10-17

    Applicant: Norinao Kouma ,  Yoshihiro Mizuno ,  Osamu Tsuboi ,  Hisao Okuda ,  Hiromitsu Soneda ,  Satoshi Ueda ,  Ippei Sawaki ,  Yoshitaka Nakamura

    Inventor： Norinao Kouma ,  Yoshihiro Mizuno ,  Osamu Tsuboi ,  Hisao Okuda ,  Hiromitsu Soneda ,  Satoshi Ueda ,  Ippei Sawaki ,  Yoshitaka Nakamura

    IPC: H01L21/00

    CPC classification number: B81C1/00182 ,  B81B2201/0235 ,  B81B2201/033 ,  B81B2201/042 ,  B81C2201/014 ,  B81C2201/0174 ,  G02B26/0841

    Abstract: A method is for manufacturing a microstructure having a thin-walled portion with use of a material substrate. The material substrate has a laminated structure which includes a first conductor layer 101, a second conductor layer 102, a third conductor layer 103, a first insulating layer 104 interposed between the first conductor layer and the second conductor layer, and a second insulating layer 105 interposed between the second conductor layer and the third conductor layer. The first insulating layer is patterned to have a first masking part for covering a thin-wall forming region of the second conductor layer. The second insulating layer is patterned to have a second masking part for covering the thin-wall forming region of the second conductor layer. The method includes forming the thin-walled portion in the second conductor portion by etching the material substrate from the first conductor layer down to the second insulating layer via a mask pattern 58 including a non-masking region corresponding to the thin-wall forming region of the second conductor layer.

    Abstract translation: 一种使用材料基板制造具有薄壁部分的微结构的方法。 材料基板具有包括第一导体层101，第二导体层102，第三导体层103，插入在第一导体层和第二导体层之间的第一绝缘层104和第二绝缘层105的层叠结构 插入在第二导体层和第三导体层之间。 第一绝缘层被图案化以具有用于覆盖第二导体层的薄壁形成区域的第一掩模部分。 图案化第二绝缘层以具有用于覆盖第二导体层的薄壁形成区域的第二掩模部分。 该方法包括：通过掩模图案58将材料基板从第一导体层蚀刻到第二绝缘层，从而在第二导体部分中形成薄壁部分，掩模图案58包括对应于薄壁形成区域的非屏蔽区域 第二导体层。

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