公开(公告)号：US11257718B2

公开(公告)日：2022-02-22

申请号：US16780046

申请日：2020-02-03

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Chanro Park ,  Stan Tsai

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L27/088 ,  H01L29/45 ,  H01L29/06 ,  H01L21/285 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The method includes: recessing an isolation region between adjacent gate structures and below metallization overburden of source/drain metallization; planarizing the metallization overburden to a level of the adjacent gate structures; and forming source/drain contacts to the source/drain metallization, on sides of and extending above the adjacent gate structures.

公开(公告)号：US11257672B2

公开(公告)日：2022-02-22

申请号：US15978334

申请日：2018-05-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nan Wu

IPC: H01L21/027 ,  H01L21/475 ,  H01L27/11 ,  H01L21/28

Abstract: The present disclosure provides manufacturing techniques in which the layout pattern of a RAM cell may be obtained on the basis of a single lithography step, followed by a sequence of two deposition processes, thereby resulting in a self-aligned mechanism for providing the most critical lateral dimensions for active regions. In this manner, the smallest pitch of approximately 80 nm and even less may be accomplished with superior device uniformity, while at the same time reducing overall manufacturing complexity.

公开(公告)号：US11243350B2

公开(公告)日：2022-02-08

申请号：US16817582

申请日：2020-03-12

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Yusheng Bian ,  Bo Peng ,  Michal Rakowski

IPC: G02B6/122 ,  G02B6/12

Abstract: The present disclosure generally relates to semiconductor devices for use in optoelectronic/photonic applications and integrated circuit (IC) chips. More particularly, the present disclosure relates to semiconductor devices having a reflector and a photonic component and a method of forming the same. The present disclosure provides a semiconductor device having a substrate, a photonic component arranged above the substrate, a bottom reflector arranged above the substrate and positioned below the photonic component, in which the bottom reflector has a plurality of grating structures configured to reflect electromagnetic waves towards the photonic component, and a top reflector arranged above the photonic component, in which the top reflector has a plurality of grating structures configured to reflect electromagnetic waves towards the photonic component.

公开(公告)号：US20220037309A1

公开(公告)日：2022-02-03

申请号：US16983071

申请日：2020-08-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Robert J. Gauthier, JR. ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Meng Miao ,  You Li

IPC: H01L27/02

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a doped well in a semiconductor substrate, in addition to a base region, emitter region, and collector region in the doped well. An insulative material is within the doped well, with a first end horizontally adjacent the collector region and a second end opposite the first end. A doped semiconductor region is within the doped well adjacent the second end of the insulative material. The doped semiconductor region is positioned to define an avalanche junction between the collector region and the doped semiconductor region across the doped well.

公开(公告)号：US11239633B2

公开(公告)日：2022-02-01

申请号：US16794330

申请日：2020-02-19

Applicant: GLOBALFOUNDRIES U.S. INC. ,  KHALIFA UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Ajey Poovannummoottil Jacob ,  Solomon M. Serunjogi ,  Mihai Adrian Tiberiu Sanduleanu

IPC: H01S5/042 ,  H03K7/02 ,  G02F1/03 ,  H04L25/49 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H04L25/03

Abstract: A driver circuit includes digital inputs, such as a first digital input and a second digital input. The digital inputs receive voltages at either a digital high-voltage or a digital low-voltage. The driver circuit has a clock input, an analog output, a first differential pair of transistors connected to the analog output, second differential pairs of transistors connected to the analog output, and voltage limiters connected to the clock input and the second differential pairs of transistors. The voltage limiters supply different voltages to the second differential pairs of transistors, which results in the second differential pairs of transistors providing analog signals to the analog output that are at different voltage steps at, and between, the digital high-voltage and the digital low-voltage.

公开(公告)号：US11239366B2

公开(公告)日：2022-02-01

申请号：US16776938

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Wenjun Li ,  Man Gu ,  Baofu Zhu

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/08

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a semiconductor body, a first source/drain region includes an epitaxial semiconductor layer on a first portion of the semiconductor body, and a second source/drain region is positioned in a second portion of the semiconductor body. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure. The first source/drain region has a first width, and the second source/drain region has a second width that is greater than the first width.

公开(公告)号：US11239315B2

公开(公告)日：2022-02-01

申请号：US16780494

申请日：2020-02-03

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Shiv Kumar Mishra ,  Baofu Zhu ,  Arkadiusz Malinowski ,  Kaushikee Mishra

IPC: H01L29/06 ,  H01L21/26 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/266 ,  H01L21/74 ,  H01L21/762 ,  H01L21/265

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to dual trench isolation structures and methods of manufacture. The structure includes: a doped well region in a substrate; a dual trench isolation region within the doped well region, the dual trench isolation region comprising a first isolation region of a first depth and a second isolation region of a second depth, different than the first depth; and a gate structure on the substrate and extending over a portion of the dual trench isolation region.

公开(公告)号：US20220029000A1

公开(公告)日：2022-01-27

申请号：US16934669

申请日：2020-07-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Siva P. Adusumilli ,  Vibhor Jain ,  Steven Bentley

IPC: H01L29/66 ,  H01L29/20

Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. A layer stack is formed on a semiconductor substrate comprised of a single-crystal semiconductor material. The layer stack includes a semiconductor layer comprised of a III-V compound semiconductor material. A polycrystalline layer is formed in the semiconductor substrate. The polycrystalline layer extends laterally beneath the layer stack.

公开(公告)号：US20220028971A1

公开(公告)日：2022-01-27

申请号：US16939213

申请日：2020-07-27

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Uzma RANA ,  Anthony K. STAMPER ,  Johnatan A. KANTAROVSKY ,  Steven M. SHANK ,  Siva P. ADUSUMILLI

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.

公开(公告)号：US11226231B1

公开(公告)日：2022-01-18

申请号：US16911950

申请日：2020-06-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Akhilesh R. Jaiswal ,  Ajey Poovannummoottil Jacob ,  Yusheng Bian ,  David C. Pritchard

IPC: G01J1/44 ,  H01L43/04 ,  H04N5/374 ,  H04N5/359 ,  H01L43/06 ,  G02F1/19 ,  H01L27/22

Abstract: An image sensor includes an array of optically switchable magnetic tunnel junctions (MTJs) arranged in columns and rows. The image sensor has first lines of transparent conductive material and second lines of conductive material. Each first line is in contact with the free layers of the MTJs in a corresponding row. Each second line is electrically connected to the fixed layers MTJs in a corresponding column. The first lines are concurrently exposable to radiation. The first and second lines are selectively biasable. In a global reset operation, biasing conditions are such that all MTJs are switched to an anti-parallel state. In a global sense operation, biasing conditions are such that, depending upon the intensity of radiation received at those portions of the first lines in contact with MTJs, the MTJs may switch to a parallel state. In selective read operations, biasing conditions are such that stored data values in the MTJs can be read.