公开(公告)号：US20230036484A1

公开(公告)日：2023-02-02

申请号：US17869301

申请日：2022-07-20

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Klodjan BIDAJ ,  Benjamin ARDAILLON ,  Lauriane GATEKA

IPC: G01R1/04 ,  G01R31/28

Abstract: A testing device for electronic dies includes a first support part and a second support part configured to be removably assembled with each other. The first and second support parts together define at least one housing where at least one electronic die can be arranged to be tested. The electronic die has a first surface with contacting elements. The at least one housing includes a first portion. This at least one housing is arranged to enable the at least one electronic die to occupy a first position in the housing where the first surface is spaced apart from the first portion, and is further arrange to enable the at least one electronic die to occupy a second position in the housing where the first surface bears against the first portion.

公开(公告)号：US20230034445A1

公开(公告)日：2023-02-02

申请号：US17965443

申请日：2022-10-13

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain COFFY ,  Remi BRECHIGNAC ,  Jean-Michel RIVIERE

IPC: H01L33/52 ,  H01L31/0203 ,  H01L31/0216 ,  H01L33/44 ,  H01L33/62

Abstract: An electronic device includes a first electronic component and a second electronic. Each electronic component includes a carrier substrate having a back side and a front side, an electronic chip including an integrated optical element, an overmolded transparent block encapsulating the electronic chip above the carrier substrate, and electrical connections between the electronic chip and electrical contacts of the carrier substrate. An overmolded grid encapsulates and holds the first and second electronic components. The grid is configured so that sides of the first and second electronic components are at least partially exposed.

公开(公告)号：US11568515B2

公开(公告)日：2023-01-31

申请号：US17361783

申请日：2021-06-29

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Julien Closs ,  Jean-Michel Delorme ,  Daniel Fauvarque ,  Laurent Folliot ,  Guillaume Legrain

IPC: G06N3/02 ,  G06T3/40 ,  G06N3/08

Abstract: An embodiment method for converting an initial digital image into a converted digital image, electronic chip, system and computer program product are disclosed, the initial digital image comprising a set of pixels, the pixels being associated respectively with colors, the initial digital image being acquired by an acquisition device, and the converted digital image able to be used by a neural network. The embodiment method comprises redimensioning of the initial digital image in order to obtain an intermediate digital image, the redimensioning being carried out by a reduction in the number of pixels of the initial image, modification of a format of one of the pixels of the intermediate digital image in order to obtain a converted digital image, the modification being carried out, after the redimensioning, by increasing the number of bits used to represent the color of the pixel.

公开(公告)号：US11563303B2

公开(公告)日：2023-01-24

申请号：US16569956

申请日：2019-09-13

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Research & Development) Limited

Inventor： Nicolas Moeneclaey ,  Shatabda Saha

IPC: H01S3/10 ,  H01S5/042 ,  H01S5/183 ,  H01S5/026 ,  G01S7/484 ,  G01S7/4863 ,  G01S17/10 ,  G01S7/4865 ,  H05B45/10 ,  G01S17/894 ,  H05B45/32 ,  H05B45/397

Abstract: Disclosed herein is a method of optical pulse emission including three phases. During a first phase, a capacitor is charged from a supply voltage node. During a second phase, a voltage stored on the capacitor is boosted, and then the capacitor is at least partially discharged through a light emitting device. During a third phase, the capacitor is further discharged by bypassing the light emitting device. The third phase may begin prior to an end of the second phase.

公开(公告)号：US11552777B2

公开(公告)日：2023-01-10

申请号：US17457354

申请日：2021-12-02

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Vincent Onde ,  Diarmuid Emslie ,  Patrick Valdenaire

IPC: H04L7/00

Abstract: A method for synchronizing a first time domain with a second time domain of a system on chip includes a detection of at least one periodic trigger event generated in the first time domain, the second time domain or in a third time domain; acquisitions, made at the instants of the at least one trigger event, of the current timestamp values representative of the instantaneous states of the time domain(s) other than the trigger time domain; a comparison, made in the third time domain, between differential durations between current timestamp values which are respectively acquired successively; and a synchronization of the second time domain with the first time domain, on the basis of the comparison.

公开(公告)号：US11550744B2

公开(公告)日：2023-01-10

申请号：US17229307

申请日：2021-04-13

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Jawad Benhammadi ,  Sylvain Meyer

IPC: G06F13/24 ,  G06F13/16 ,  G06F21/85 ,  H03K19/20 ,  G06F1/3237

Abstract: In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.

公开(公告)号：US11539356B2

公开(公告)日：2022-12-27

申请号：US17078317

申请日：2020-10-23

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Helene Esch ,  David Chesneau

IPC: H03K5/24 ,  G05F1/56 ,  G05F3/24 ,  H02M3/158 ,  H02M3/335 ,  H03K17/082 ,  H03K17/687 ,  H03K19/00 ,  H02M3/00

Abstract: In an embodiment, a voltage comparator includes: a first switch having a conduction terminal coupled to an internal node that is coupled to an output of the voltage comparator; a current source; a capacitor; and a second switch connected in parallel with the capacitor, wherein the current source, the capacitor, and the first switch are coupled in series.

公开(公告)号：US20220392820A1

公开(公告)日：2022-12-08

申请号：US17833153

申请日：2022-06-06

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain COFFY ,  Younes BOUTALEB

IPC: H01L23/367 ,  H01L33/64 ,  H01L31/024 ,  H01L33/58 ,  H01L31/0232 ,  H01L33/62 ,  H01L31/02 ,  H01L23/00

Abstract: A cap is mounted to a support substrate, the cap including a cap body and an optical shutter. The cap and support substrate define a housing. An electronic chip is disposed in the housing above the support substrate. A face of the electronic chip supports an optical device that is optically coupled with the optical shutter. The cap body is thermally conductive. Within the housing, a thermally conductive linking structure is coupled in a thermally conductive manner between the cap body and the electronic chip. The thermally conductive linking structure surrounds the electronic chip. A thermal interface material fills a portion of the housing between the thermally conductive linking structure and the cap body.

公开(公告)号：US11489446B2

公开(公告)日：2022-11-01

申请号：US17183721

申请日：2021-02-24

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David Chesneau

IPC: H02M3/158

Abstract: In an embodiment, a method for operating a voltage step-down switched mode power supply includes delivering an output voltage with an output stage having a power transistor that is cyclically made conducting by a first control signal. In PWM mode, the method includes generating an error voltage based on the output voltage and a reference voltage, and applying a first delay on a first control signal. The first delay is determined so as to reduce a difference between the error voltage and the reference voltage.

公开(公告)号：US11482836B2

公开(公告)日：2022-10-25

申请号：US16774889

申请日：2020-01-28

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Samuel Rigault ,  Nicolas Moeneclaey ,  Xavier Branca

IPC: H01S5/042 ,  H01S5/068

Abstract: A driver circuit includes a fly capacitor with a first end and a second end. The driver circuit includes a laser diode having an anode and a cathode. The driver circuit is configured to operate in first and second operating states. The anode is coupled to the first end of the fly capacitor. In the first operating state, the cathode is coupled to a first voltage supply node, the first end of the fly capacitor is coupled to a second voltage supply node, and the second end of the fly capacitor is coupled to a first reference terminal. In the second operating state, the cathode is coupled to a second reference terminal and decoupled from the first voltage supply node, the first end of the fly capacitor is decoupled from the second voltage supply node, and the second end of the fly capacitor is coupled to a third reference terminal.