公开(公告)号：US20210126109A1

公开(公告)日：2021-04-29

申请号：US16867867

申请日：2020-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  Shu-Yuan Ku

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.

公开(公告)号：US20210111119A1

公开(公告)日：2021-04-15

申请号：US17106766

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/288 ,  H01L23/532 ,  H01L21/027

Abstract: A semiconductor device includes a substrate, a bottom etch stop layer over the substrate, a middle etch stop layer over the bottom etch stop layer, and a top etch stop layer over the middle etch stop layer. The top, middle, and bottom etch stop layers include different material compositions from each other. The semiconductor device further includes a dielectric layer over the top etch stop layer and a via extending through the dielectric layer and the top, middle, and bottom etch stop layers. The via has a first sidewall in contact with the dielectric layer and slanted inwardly from top to bottom towards a center of the via and a second sidewall in contact with the bottom etch stop layer and slanted outwardly from top to bottom away from the center of the via.

公开(公告)号：US10854542B2

公开(公告)日：2020-12-01

申请号：US16713862

申请日：2019-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/288 ,  H01L23/532 ,  H01L21/027 ,  H01L21/321 ,  H01L29/06

Abstract: A method includes providing a substrate, wherein the substrate includes a conductive feature in a top portion of the substrate; forming a buffer layer over the substrate; forming a dielectric layer over the buffer layer; performing a first etching process to form an opening in the dielectric layer, thereby exposing a top surface of the buffer layer; and performing a second etching process to extend the opening downwardly into the buffer layer, thereby exposing a top surface of the conductive feature, wherein the performing of the second etching process includes laterally enlarging a footing profile of the opening.

公开(公告)号：US10811506B2

公开(公告)日：2020-10-20

申请号：US16404017

申请日：2019-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin ,  Che-Cheng Chang ,  Horng-Huei Tseng

IPC: H01L21/02 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/40 ,  H01L29/51

Abstract: A method includes receiving a device having a substrate and a first dielectric layer surrounding a gate trench. The method further includes depositing a gate dielectric layer and a gate work function (WF) layer in the gate trench and forming a hard mask (HM) layer in a space in the gate trench and surrounded by the gate WF layer. The method further includes recessing the gate WF layer such that a top surface of the gate WF layer in the gate trench is below a top surface of the first dielectric layer. After the recessing of the gate WF layer, the method further includes removing the HM layer in the gate trench and depositing a metal layer in the gate trench. The metal layer is in physical contact with a sidewall surface of the gate WF layer that is deposited before the HM layer is formed.

公开(公告)号：US20200294859A1

公开(公告)日：2020-09-17

申请号：US16883486

申请日：2020-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

Abstract: An embodiment is a method including forming a multi-layer stack over a substrate, the multi-layer stack including alternating first layers and second layers, patterning the multi-layer stack to form a fin, forming an isolation region surrounding the fin, an upper portion of the fin extending above a top surface of the isolation region, forming a gate stack on sidewalls and a top surface of the upper portion of the fin, the gate stack defining a channel region of the fin, and removing the first layers from the fin outside of the gate stack, where after the removing the first layers, the channel region of the fin includes both the first layers and the second layers.

公开(公告)号：US10763258B2

公开(公告)日：2020-09-01

申请号：US15990807

申请日：2018-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/092 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/3215 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

Abstract: An integrated circuit includes a substrate, at least one n-type semiconductor device, and at least one p-type semiconductor device. The n-type semiconductor device is present on the substrate. The n-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle. The p-type semiconductor device is present on the substrate. The p-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device.

公开(公告)号：US10748912B2

公开(公告)日：2020-08-18

申请号：US16046369

申请日：2018-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin ,  Che-Cheng Chang ,  Horng-Huei Tseng

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/11582 ,  H01L49/02 ,  H01L21/3065 ,  H01L21/8234 ,  H01L29/165

Abstract: A method of forming a semiconductor device includes receiving a substrate with a plurality of gate structures; forming spacers on sidewalls of the gate structures; evaluating a pitch variation to the gate structures; determining an etch recipe according to the pitch variation; performing an etch process to source/drain regions associated with the gate structures using the etch recipe, thereby forming source/drain recesses with respective depths; and performing an epitaxy growth to form source/drain features in the source/drain recesses using a semiconductor material.

公开(公告)号：US10692701B2

公开(公告)日：2020-06-23

申请号：US15460771

申请日：2017-03-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin Chen ,  Tung-Wen Cheng ,  Che-Cheng Chang ,  Jr-Jung Lin ,  Chih-Han Lin

IPC: H01L21/8234 ,  H01J37/32 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/78 ,  H01L21/67

Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.

公开(公告)号：US10679989B2

公开(公告)日：2020-06-09

申请号：US16166762

申请日：2018-10-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin ,  Che-Cheng Chang ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8234

Abstract: An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a second gate structure. A source/drain region is disposed between the first gate structure and the second gate structure. A first ILD layer is disposed between the first spacers and the second spacers. A portion of the first ILD layer has a first recessed upper surface. A dielectric layer is disposed over the first spacers, the second spacers, and the first recessed upper surface of the first ILD layer. A portion of the dielectric layer has a second recessed upper surface that is disposed over the portion of the first ILD layer having the first recessed upper surface. A second ILD layer is disposed over the dielectric layer. A contact extends through the second ILD layer, the dielectric layer, and the first ILD layer to the source/drain region.

公开(公告)号：US10672908B2

公开(公告)日：2020-06-02

申请号：US16207218

申请日：2018-12-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.