公开(公告)号：US20160285509A1

公开(公告)日：2016-09-29

申请号：US14984966

申请日：2015-12-30

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Mark WALLIS ,  Yoann BOUVET ,  Pierre DEMAJ

IPC: H04B3/54 ,  H04L27/26 ,  H04L5/00

CPC classification number: H04B3/54 ,  H04L5/0007 ,  H04L25/03993 ,  H04L25/067 ,  H04L27/2607 ,  H04L27/2656 ,  H04L27/2675 ,  H04L27/2691

Abstract: A method is for processing an analog signal coming from a transmission channel. The analog signal may include a useful signal modulated on a sub-set of carriers. The method may include analog-to-digital converting of the analog signal into a digital signal, and synchronization processing the digital signal. The synchronizing may include determining, in a time domain, a limited number of coefficients of a predictive filter from an autoregressive model of the digital signal, and filtering the digital signal in the time domain by a digital finite impulse response filter with coefficients based upon the limited number of coefficients to provide a filtered digital signal. The method may include detecting of an indication allowing a location in the frame structure to be identified, using the filtered digital signal and a reference signal.

Abstract translation: 一种用于处理来自传输信道的模拟信号的方法。 模拟信号可以包括调制在载波子集上的有用信号。 该方法可以包括将模拟信号模数转换为数字信号，并对数字信号进行同步处理。 同步可以包括在时域中从数字信号的自回归模型中确定预测滤波器的有限数量的系数，并且通过数字有限脉冲响应滤波器在时域中对数字信号进行滤波，其中系数基于 有限数量的系数提供一个滤波后的数字信号。 该方法可以包括使用滤波的数字信号和参考信号来检测允许帧结构中的位置被识别的指示。

公开(公告)号：US09454163B2

公开(公告)日：2016-09-27

申请号：US14612063

申请日：2015-02-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Jimmy Fort ,  Thierry Soude

IPC: G05F1/46 ,  G05F3/30

CPC classification number: G05F3/267 ,  G05F1/468 ,  G05F3/30

Abstract: According to an embodiment, generating an adjustable bandgap reference voltage includes generating a current proportional to absolute temperature (PTAT). Generating the PTAT current includes equalizing voltages across the terminals of a core that is designed to be traversed by the PTAT current. Generating the adjustable bandgap reference also includes generating a current inversely proportional to absolute temperature (CTAT), summing the PTAT and the CTAT currents and generating the bandgap reference voltage based on the sum of the currents. Equalizing includes connecting-across the terminals of the core a first fed-back amplifier with at least one first stage arranged as a folded setup and including first PMOS transistors arranged according to a common-gate setup. Equalizing also includes biasing the first stage based on the CTAT current. The summation of the PTAT and CTAT currents is performed in the feedback stage of the first amplifier.

公开(公告)号：US20160188900A1

公开(公告)日：2016-06-30

申请号：US15060159

申请日：2016-03-03

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yannick Teglia

IPC: G06F21/62 ,  G06F21/56

CPC classification number: G06F21/6218 ,  G06F12/1425 ,  G06F12/1483 ,  G06F21/561 ,  G06F21/566 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2221/034

Abstract: A method for protecting a volatile memory against a virus, wherein: rights of writing, reading, or execution are assigned to certain areas of the memory; and a first list of opcodes authorized or forbidden as a content of the areas is associated with each of these areas.

公开(公告)号：US09351164B2

公开(公告)日：2016-05-24

申请号：US14633913

申请日：2015-02-27

Applicant: STMicroelectronics (Rousset) SAS ,  Proton World International N.V.

Inventor： Olivier Van Nieuwenhuyze ,  Christophe Henri Ricard

IPC: H04W12/08 ,  H04L29/06 ,  H04W12/06 ,  H04W12/12 ,  H04W4/00

CPC classification number: H04W12/08 ,  H04L63/0492 ,  H04W4/80 ,  H04W12/06 ,  H04W12/12

Abstract: A processing device of an NFC device receives a request, initiated by a first application loaded in a memory of the NFC device, to modify one or more parameters of an NFC routing table of an NFC router of the NFC device. The NFC routing table has parameters indicating the devices to which NFC messages are to be routed. The processing device retrieves a first identifier associated with the application and transmits the first identifier to the NFC router. The NFC router, based on the first identifier, verifies whether or not the application is authorized to modify the routing table.

Abstract translation: NFC设备的处理设备接收由加载在NFC设备的存储器中的第一应用启动的请求，以修改NFC设备的NFC路由器的NFC路由表的一个或多个参数。 NFC路由表具有指示NFC消息要路由到的设备的参数。 处理设备检索与应用相关联的第一标识符，并将第一标识符发送到NFC路由器。 NFC路由器基于第一标识符来验证应用是否被授权修改路由表。

公开(公告)号：US09331027B2

公开(公告)日：2016-05-03

申请号：US13959496

申请日：2013-08-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L23/34 ,  H01L23/00

CPC classification number: H01L23/576 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes active circuitry disposed at a surface of a semiconductor body and an interconnect region disposed above the semiconductor body. A thermoelectric material is disposed in an upper portion of the interconnect region away from the semiconductor body. The thermoelectric material is configured to deliver electrical energy when exposed to a temperature gradient. This material can be used, for example, in a method for detecting the repackaging of the integrated circuit after it has been originally packaged.

Abstract translation: 集成电路包括设置在半导体主体的表面的有源电路和设置在半导体主体上方的互连区域。 热电材料设置在互连区域的远离半导体本体的上部。 热电材料被配置为当暴露于温度梯度时传递电能。 该材料可以用于例如在最初封装集成电路的重新包装检测方法之后。

公开(公告)号：US20160107886A1

公开(公告)日：2016-04-21

申请号：US14985083

申请日：2015-12-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Antonio di-Giacomo ,  Brice Arrazat

IPC: B81C1/00 ,  H01H57/00

Abstract: Methods of forming and operating a switching device are provided. The switching device is formed in an interconnect, the interconnect including a plurality of metallization levels, and has an assembly that includes a beam held by a structure. The beam and structure are located within the same metallization level. Locations of fixing of the structure on the beam are arranged so as to define for the beam a pivot point situated between these fixing locations. The structure is substantially symmetric with respect to the beam and to a plane perpendicular to the beam in the absence of a potential difference. The beam is able to pivot in a first direction in the presence of a first potential difference applied between a first part of the structure and to pivot in a second direction in the presence of a second potential difference applied between a second part of the structure.

Abstract translation: 提供了形成和操作开关装置的方法。 开关装置形成在互连中，互连包括多个金属化层，并且具有包括由结构保持的梁的组件。 梁和结构位于相同的金属化水平内。 布置结构在梁上的固定位置，以便为梁定义位于这些固定位置之间的枢转点。 该结构在不存在电位差的情况下相对于光束和垂直于光束的平面基本对称。 在存在施加在结构的第一部分之间的第一电位差并且在存在施加在结构的第二部分之间的第二电位差的情况下在第二方向上枢转时，梁能够在第一方向上枢转。

公开(公告)号：US20160079391A1

公开(公告)日：2016-03-17

申请号：US14946408

申请日：2015-11-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L21/225 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66666 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/2253 ,  H01L21/2257 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/10876 ,  H01L27/2454 ,  H01L29/0676 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7883 ,  H01L29/7889 ,  H01L29/7926

Abstract: The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.

Abstract translation: 本发明涉及一种制造垂直MOS晶体管的方法，包括以下步骤：在半导体表面之上形成至少一个电介质层中的导电层; 通过至少导电层蚀刻孔，所述孔暴露所述导电层的内侧边缘和所述半导体表面的一部分; 在导电层的内侧边缘上形成栅极氧化物，在半导体表面的部分上形成底部氧化物; 在所述孔的侧边缘上形成蚀刻保护侧壁，所述侧壁覆盖所述栅极氧化物和所述底部氧化物的外部区域，留下所述底部氧化物的内部区域; 蚀刻底部氧化物的暴露的内部区域，直到达到半导体表面; 以及在所述孔中沉积半导体材料。

公开(公告)号：US09269771B2

公开(公告)日：2016-02-23

申请号：US14627281

申请日：2015-02-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Guilhem Bouton ,  Pascal Fornara

IPC: H01L29/10 ,  H01L29/06 ,  H01L21/762 ,  H01L21/763 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/11293 ,  H01L29/0649 ,  H01L29/78 ,  H01L29/7846

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

Abstract translation: 集成电路包括衬底和至少一个对压缩应力非常敏感的部件，其至少部分地布置在由绝缘区域限制的衬底的有源区域内。 为了解决有源区域中的压缩应力，电路还包括位于至少绝缘区域中的至少一个电惰性沟槽，并且包含被配置为减小有源区域中的压缩应力的内部区域。 内部填充多晶硅。 多晶硅填充沟槽可以进一步延伸穿过绝缘区域并进入衬底。

公开(公告)号：US20160007202A1

公开(公告)日：2016-01-07

申请号：US14850676

申请日：2015-09-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Charles

IPC: H04W12/08 ,  H04W4/00 ,  H04W12/06 ,  G06Q20/32

CPC classification number: H04W12/08 ,  G06Q20/3227 ,  G06Q20/3229 ,  H04M1/67 ,  H04M1/7253 ,  H04M2250/04 ,  H04W4/80 ,  H04W12/06

Abstract: A method and a device for protecting a security module connected to a near-field communication router in a telecommunication device, wherein a transmission between the router and the security module is only allowed in the presence of a radio frequency communication flow detected by the router.

Abstract translation: 一种用于保护连接到电信设备中的近场通信路由器的安全模块的方法和设备，其中仅在由路由器检测到的射频通信流存在的情况下才允许路由器与安全模块之间的传输。

公开(公告)号：US20150346275A1

公开(公告)日：2015-12-03

申请号：US14824893

申请日：2015-08-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: G01R31/28

CPC classification number: G01R31/2872 ,  G01L1/00 ,  G01L1/005 ,  G01L1/148 ,  G01L1/225 ,  G01L1/2293 ,  G01L11/00 ,  G01L25/00 ,  G01R31/2884 ,  H01L27/06 ,  H01L29/66007

Abstract: A method for manufacturing an integrated circuit includes forming in a substrate a measuring circuit sensitive to mechanical stresses and configured to supply a measurement signal representative of mechanical stresses exerted on the measuring circuit. The measuring circuit is positioned such that the measurement signal is also representative of mechanical stresses exerted on a functional circuit of the integrated circuit. A method of using the integrated circuit includes determining from the measurement signal the value of a parameter of the functional circuit predicted to mitigate an impact of the variation in mechanical stresses on the operation of the functional circuit, and supplying the functional circuit with the determined value of the parameter.

Abstract translation: 一种用于制造集成电路的方法包括在基板上形成对机械应力敏感的测量电路，并且被配置为提供表示施加在测量电路上的机械应力的测量信号。 测量电路被定位成使得测量信号也代表施加在集成电路的功能电路上的机械应力。 使用集成电路的方法包括从测量信号确定预测的功能电路的参数的值，以减轻机械应力的变化对功能电路的操作的影响，以及向功能电路提供确定的值 的参数。