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    SUB-BANDGAP COMPENSATED REFERENCE VOLTAGE GENERATION CIRCUIT
    264.
    发明申请
    SUB-BANDGAP COMPENSATED REFERENCE VOLTAGE GENERATION CIRCUIT 审中-公开

    公开(公告)号：US20200073430A1

    公开(公告)日：2020-03-05

    申请号：US16558717

    申请日：2019-09-03

    Applicant: STMicroelectronics International N.V.

    Inventor： Pijush Kanti PANJA ,  Gautam Dey KANUNGO

    IPC: G05F3/26

    Abstract: A sub-bandgap reference voltage generator includes a reference current generator generating a reference current (proportional to absolute temperature), a voltage generator generating an input voltage (proportional to absolute temperature) from the reference current, and a differential amplifier. The differential amplifier is biased by the reference current and has an input receiving the input voltage and a resistor generating a voltage proportional to absolute temperature summed with the input voltage to produce a temperature insensitive output reference voltage. The reference current generator may generate the reference current as a function of a difference between bias voltages of first and second transistors. The voltage generator may generate the input voltage by applying the current proportional to absolute temperature through a plurality of transistors coupled in series between the bias voltage of the second transistor and ground, and tapping a node between given adjacent ones of the plurality of transistors.

    Use of a raw oscillator and frequency locked loop to quicken lock time of frequency locked loop
    265.
    发明授权
    Use of a raw oscillator and frequency locked loop to quicken lock time of frequency locked loop 有权

    公开(公告)号：US10566980B2

    公开(公告)日：2020-02-18

    申请号：US15924584

    申请日：2018-03-19

    Applicant: STMicroelectronics International N.V.

    Inventor： Nitin Gupta ,  Jeet Narayan Tiwari

    IPC: H03L7/07 ,  H03L7/099 ,  H03L7/095

    Abstract: Disclosed is a method of locking a locked loop quickly, including receiving an input signal having an input frequency, and generating an intermediate signal having an intermediate frequency intended to be equal to a geometric mean of the input frequency and a desired frequency, but not equal. Results of division of the desired output frequency by the intermediate frequency are estimated, producing a first divider value. A first locked loop utilizing a controllable oscillator is activated. A divider value of the first locked loop is set to the first divider value, and the intermediate signal is provided to the first locked loop, so that when the first locked loop reaches lock, the controllable oscillator produces the desired frequency. When the first locked loop reaches lock, a second locked loop that utilizes the controllable oscillator is activated, the first locked loop is deactivated, and generation of the intermediate signal is ceased.

    Voltage regulator bypass circuitry usable during device testing operations
    266.
    发明授权
    Voltage regulator bypass circuitry usable during device testing operations 有权

    公开(公告)号：US10527672B2

    公开(公告)日：2020-01-07

    申请号：US15713168

    申请日：2017-09-22

    Applicant: STMicroelectronics International N.V.

    Inventor： Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

    IPC: G01R31/28 ,  H03K19/20

    Abstract: Disclosed herein is circuitry for bypassing a medium voltage regulator during testing. The circuitry includes a low voltage regulator to, in operation, generate a first voltage within a first voltage range for powering first circuitry, and a medium voltage regulator to, in operation, generate a second voltage within a second voltage range greater than the first voltage range for powering second circuitry. A low voltage regulator bypass circuit generates a low voltage regulator bypass signal that operates to selectively bypass the low voltage regulator. A medium voltage regulator bypass circuit bypasses the medium voltage regulator as a function of the low voltage regulator bypass signal and an external voltage regulator select signal, the bypass of the medium voltage regulator being such that an external voltage can be applied to the second circuitry.

    VOLTAGE MULTIPLIER CIRCUIT WITH A COMMON BULK AND CONFIGURED FOR POSITIVE AND NEGATIVE VOLTAGE GENERATION
    267.
    发明申请
    VOLTAGE MULTIPLIER CIRCUIT WITH A COMMON BULK AND CONFIGURED FOR POSITIVE AND NEGATIVE VOLTAGE GENERATION 审中-公开

    公开(公告)号：US20190393779A1

    公开(公告)日：2019-12-26

    申请号：US16563069

    申请日：2019-09-06

    Applicant: STMicroelectronics International N.V.

    Inventor： Vikas RANA

    IPC: H02M3/07 ,  H03K19/096 ,  G05F1/10

    Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.

    BIASING CASCODE TRANSISTORS OF AN OUTPUT BUFFER CIRCUIT FOR OPERATION OVER A WIDE RANGE OF SUPPLY VOLTAGES
    268.
    发明申请
    BIASING CASCODE TRANSISTORS OF AN OUTPUT BUFFER CIRCUIT FOR OPERATION OVER A WIDE RANGE OF SUPPLY VOLTAGES 审中-公开

    公开(公告)号：US20190312575A1

    公开(公告)日：2019-10-10

    申请号：US16253410

    申请日：2019-01-22

    Applicant: STMicroelectronics International N.V.

    Inventor： Manoj Kumar Kumar TIWARI ,  Saiyid Mohammad Irshad RIZVI

    IPC: H03K17/082 ,  H03K17/687 ,  G05F3/16 ,  H03K19/0185

    Abstract: An output stage of an output buffer circuit includes a first drive transistor and a first cascode transistor (coupled in series between a first supply node and an output node) and a second drive transistor and a second cascode transistor (coupled in series between the output node and a second supply node). Gates of the first and second cascode transistors are biased with first and second bias voltages, respectively. The first bias voltage equals the first supply voltage at the first supply node when the first supply voltage is less than a threshold, and is fixed at a fixed voltage for any first supply voltage exceeding the threshold voltage. The second bias voltage equals a fixed voltage when the first supply voltage is less than a threshold voltage, and is offset from the first supply voltage by a fixed difference for any first supply voltage exceeding the threshold.

    Tool to create a reconfigurable interconnect framework
    270.
    发明授权
    Tool to create a reconfigurable interconnect framework 有权

    公开(公告)号：US10417364B2

    公开(公告)日：2019-09-17

    申请号：US15423292

    申请日：2017-02-02

    Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Thomas Boesch ,  Giuseppe Desoli

    IPC: G06F17/50 ,  G06N3/04 ,  G06N3/08 ,  G06N3/063 ,  G06F9/445 ,  G06F13/40 ,  G06F15/78

    Abstract: Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs. The input port architectural composition is defined by a plurality of M data paths including A data inputs and B control inputs.

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