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    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
    263.
    发明申请
    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM 有权

    公开(公告)号：US20220027275A1

    公开(公告)日：2022-01-27

    申请号：US17492776

    申请日：2021-10-04

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  Kai Chirca ,  David Matthew Thompson

    IPC: G06F12/0842 ,  G06F12/0811 ,  G06F12/0888 ,  G06F1/14 ,  G06F9/54

    Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

    Memory pipeline control in a hierarchical memory system
    266.
    发明授权
    Memory pipeline control in a hierarchical memory system 有权

    公开(公告)号：US11138117B2

    公开(公告)日：2021-10-05

    申请号：US16879264

    申请日：2020-05-20

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  Kai Chirca ,  David Matthew Thompson

    IPC: G06F12/00 ,  G06F12/0842 ,  G06F12/0811 ,  G06F12/0888 ,  G06F1/14 ,  G06F9/54

    Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

    SYSTEM AND METHOD TO CONTROL THE NUMBER OF ACTIVE VECTOR LANES IN A PROCESSOR
    269.
    发明申请
    SYSTEM AND METHOD TO CONTROL THE NUMBER OF ACTIVE VECTOR LANES IN A PROCESSOR 有权

    公开(公告)号：US20210109753A1

    公开(公告)日：2021-04-15

    申请号：US17126156

    申请日：2020-12-18

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy David Anderson ,  Duc Quang Bui

    IPC: G06F9/30 ,  G06F1/3206 ,  G06F1/3287 ,  G06F9/38

    Abstract: In one disclosed embodiment, a processor includes a first execution unit and a second execution unit, a register file, and a data path including a plurality of lanes. The data path and the register file are arranged so that writing to the register file by the first execution unit and by the second execution unit is allowed over the data path, reading from the register file by the first execution unit is allowed over the data path, and reading from the register file by the second execution unit is not allowed over the data path. The processor also includes a power control circuit configured to, when a transfer of data between the register file and either of the first and second execution units uses less than all of the lanes, power down the lanes of the data path not used for the transfer of the data.

    METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-ALIGNED WRITES
    270.
    发明申请
    METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-ALIGNED WRITES 审中-公开

    公开(公告)号：US20200371946A1

    公开(公告)日：2020-11-26

    申请号：US16882234

    申请日：2020-05-22

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

    IPC: G06F12/0888 ,  G06F12/0891 ,  G06F12/02 ,  G06F9/54

    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to reduce read-modify-write cycles for non-aligned writes. An example apparatus includes a memory that includes a plurality of memory banks, an interface configured to be coupled to a central processing unit, the interface to obtain a write operation from the central processing unit, wherein the write operation is to write a subset of the plurality of memory banks, and bank processing logic coupled to the interface and to the memory, the bank processing logic to determine the subset of the plurality of memory banks to write based on the write operation, and determine whether to cause a read operation to be performed in response to the write operation based on whether a number of addresses in the subset of the plurality of memory banks to write satisfies a threshold.

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