公开(公告)号：US5568418A

公开(公告)日：1996-10-22

申请号：US447772

申请日：1995-05-23

Applicant: Giuseppe Crisenza ,  Cesare Clementi

Inventor： Giuseppe Crisenza ,  Cesare Clementi

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  G11C11/34

CPC classification number: H01L27/11526 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L27/115

Abstract: A method comprising the steps of depositing a first and second polysilicon layer, separated by an oxide layer; selectively etching the second polysilicon layer to form first gate regions; forming first substrate regions in the substrate and laterally in relation to the first gate regions; selectively etching the first polysilicon layer to form second gate regions of a length greater than the first gate regions; and forming in the substrate, laterally in relation to the second gate regions and partially overlapping the first substrate regions, second substrate regions of a higher doping level than the first substrate regions.

Abstract translation: 一种方法，包括沉积由氧化物层分离的第一和第二多晶硅层的步骤; 选择性地蚀刻第二多晶硅层以形成第一栅极区; 在所述衬底中形成第一衬底区域并相对于所述第一栅极区域侧向地形成; 选择性地蚀刻第一多晶硅层以形成长度大于第一栅极区域的第二栅极区域; 以及在所述衬底中相对于所述第二栅极区域横向地形成并且部分地与所述第一衬底区域重叠的第二衬底区域具有比所述第一衬底区域更高的掺杂水平。

公开(公告)号：US5566114A

公开(公告)日：1996-10-15

申请号：US349783

申请日：1994-12-06

Applicant: Luigi Pascucci ,  Carla M. Golla

Inventor： Luigi Pascucci ,  Carla M. Golla

IPC: H01L21/82 ,  G11C29/00 ,  H01L27/10 ,  G11C7/00

CPC classification number: G11C29/70

Abstract: A redundancy circuitry for a semiconductor memory device comprising a matrix of memory elements and a plurality of programmable non-volatile memory registers. The non-volatile memory registers being programmable to store addresses of defective memory elements that must be replaced by redundancy memory elements. The redundancy circuitry comprises a combinatorial circuit supplied by address signals and supplying the non-volatile registers with an inhibition signal for inhibiting the selection of redundancy memory elements when a memory element of the matrix is addressed whose address coincides with the address stored in a non-programmed memory register.

Abstract translation: 一种用于半导体存储器件的冗余电路，包括存储元件矩阵和多个可编程非易失性存储寄存器。 非易失性存储器寄存器是可编程的，以存储必须由冗余存储器元件替代的缺陷存储器元件的地址。 冗余电路包括由地址信号提供的组合电路，并且当矩阵的存储元件被寻址时，向非易失性寄存器提供用于禁止冗余存储器元件的选择的禁止信号，其地址与存储在非易失性寄存器中的地址一致， 程序存储器寄存器。

公开(公告)号：US5559687A

公开(公告)日：1996-09-24

申请号：US261473

申请日：1994-06-17

Applicant: Germano Nicollini ,  Pierangelo Confalonieri ,  Carlo Crippa

Inventor： Germano Nicollini ,  Pierangelo Confalonieri ,  Carlo Crippa

IPC: G11C17/00 ,  G11C16/06 ,  H02M3/07 ,  H02M9/04 ,  H02M3/18

CPC classification number: H02M3/07

Abstract: A voltage multiplier for relatively high output current has its design output voltage stabilized and rendered independent of process spread, temperature, supply voltage and output current level, by a stabilization loop driving the switch that cyclically connects to ground a charge transfer capacitance of the functional voltage multiplier circuit. The feedback loop comprises an integrating stage, stabilized by creating a low-frequency zero in the transfer function for compensating one of two low-frequency poles of the transfer function of the whole circuit.

Abstract translation: 用于相对较高输出电流的电压倍增器，其设计输出电压稳定并且独立于工艺扩展，温度，电源电压和输出电流电平，通过稳定环路驱动开关，循环地连接到接地的功能电压的电荷转移电容 乘法器电路。 反馈回路包括积分级，通过在传递函数中产生低频零点来稳定，以补偿整个电路的传递函数的两个低频极点中的一个。

公开(公告)号：US5559449A

公开(公告)日：1996-09-24

申请号：US391149

申请日：1995-02-21

Applicant: Silvia Padoan ,  Luigi Pascucci

Inventor： Silvia Padoan ,  Luigi Pascucci

IPC: G11C17/00 ,  G11C16/06 ,  H01L27/10 ,  H03K19/177 ,  H03K19/173

CPC classification number: H03K19/1772

Abstract: The PLA, which implements a state machine of a nonvolatile memory, presents a dynamic NAND-NOT-NOR configuration, and the timing signals for correct reading of the PLA are generated by a clock generator which generates a monostable succession of read enabling signals on receiving a predetermined switching edge of an external clock signal. The clock generator enables evaluation of the AND and OR planes of the PLA and subsequently storage of the results through sections duplicating the propagation delays of the signals in the corresponding parts of the PLA. Reading is terminated as soon as completion of the storage step is indicated, so that reading of the PLA lasts only as long as strictly necessary, thus preventing erroneous switching while at the same time ensuring correct reading of the PLA.

Abstract translation: 实现非易失性存储器的状态机的PLA呈现动态NAND非NOT-NOR配置，并且用于正确读取PLA的定时信号由时钟发生器产生，时钟发生器在接收时产生单个可读序列的读使能信号 外部时钟信号的预定开关沿。 时钟发生器可以评估PLA的AND和OR平面，然后通过复制PLA中相应部分的信号的传播延迟的部分来存储结果。 一旦完成存储步骤，阅读就会被终止，因此只要严格必要时，解放军的阅读时间就会持续下去，从而防止错误切换，同时确保PLA的正确阅读。

公开(公告)号：US5546054A

公开(公告)日：1996-08-13

申请号：US377524

申请日：1995-01-20

Applicant: Marco Maccarrone ,  Marco Olivo ,  Carla M. Golla

Inventor： Marco Maccarrone ,  Marco Olivo ,  Carla M. Golla

IPC: G11C17/00 ,  G05F3/24 ,  G05F3/26 ,  H03F1/30 ,  H03B5/24 ,  G05F3/16 ,  H03K3/011 ,  H03K3/03

CPC classification number: G05F3/262

Abstract: A current source including a current mirror circuit and an active load circuit which form a reference branch, for setting a reference current value, and a mirroring branch, defining an output current value, connected between supply and ground. A voltage stabilizing transistor is interposed between the current mirror circuit and the load circuit in the reference branch only, and is so biased as to maintain its gate terminal at a predetermined voltage. As such, the potential with respect to ground of the drain terminal of the reference branch load transistor is fixed, so that its drain-source voltage drop (and the current through it) is substantially independent of supply voltage. The current source may be used to advantage in an oscillator for generating the: clock signal of a nonvolatile memory.

Abstract translation: 电流源包括形成用于设定参考电流值的参考支路的电流镜电路和有源负载电路以及连接在电源和地之间的限定输出电流值的镜像支路。 稳压晶体管仅插入在电流镜电路和参考支路中的负载电路之间，并被偏置以将其栅极端子保持在预定电压。 因此，参考分支负载晶体管的漏极端子的接地电位是固定的，使得其漏 - 源电压降（和通过它的电流）基本上不依赖于电源电压。 在振荡器中可以使用电流源来产生非易失性存储器的：时钟信号。

公开(公告)号：US5546044A

公开(公告)日：1996-08-13

申请号：US311941

申请日：1994-09-26

Applicant: Cristiano Calligaro ,  Roberto Gastaldi ,  Piero Malcovati ,  Guido Torelli

Inventor： Cristiano Calligaro ,  Roberto Gastaldi ,  Piero Malcovati ,  Guido Torelli

IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  H01L21/822 ,  H01L27/04 ,  H02M3/07 ,  H03K19/0175 ,  G05F1/10

CPC classification number: H02M3/07 ,  G11C5/145

Abstract: A circuit for generating positive and negative boosted voltages, comprising first and second voltage booster circuits, respectively for positive and negative voltages, which have output terminals interconnected at a common node. It comprises two tristate logic gate circuits for coupling said voltage booster circuits to a positive supply voltage generator and additional tristate logic gate circuits for driving the phases of charge pump circuits incorporated into the booster circuits. This voltage generating circuit may be integrated in single-well CMOS technology.

Abstract translation: 用于产生正和负升压电压的电路，包括分别用于正电压和负电压的第一和第二升压电路，其具有在公共节点处互连的输出端子。 它包括两个三态逻辑门电路，用于将所述升压电路耦合到正电源电压发生器和用于驱动并入升压电路的电荷泵电路的相位的附加三态逻辑门电路。 该电压产生电路可以集成在单阱CMOS技术中。

公开(公告)号：US5544085A

公开(公告)日：1996-08-06

申请号：US309793

申请日：1994-09-21

Applicant: Mauro L. Sali ,  Carla Golla

Inventor： Mauro L. Sali ,  Carla Golla

IPC: G06F7/509 ,  G06F7/50

CPC classification number: G06F7/509

Abstract: A fast adder chain for adding together at least one pair of digital words and including a plurality of cascaded adder blocks. Each block having computation adders for obtaining the pseudosum of said pair of digital words and latches for storing and transmitting the pseudosum to the next block and the pseudocarry from the computation to the chain end.

Abstract translation: 一种用于将至少一对数字字相加并包括多个级联加法器块的快速加法器链。 每个块具有计算加法器，用于获得所述数字字对和伪锁存器的伪脉冲，用于存储并将伪随机数传送到下一个数据块，并且伪运算从计算到链结。

公开(公告)号：US5541456A

公开(公告)日：1996-07-30

申请号：US259968

申请日：1994-06-14

Applicant: Giampietro Maggioni ,  Marco Morelli

Inventor： Giampietro Maggioni ,  Marco Morelli

IPC: H02J7/24 ,  H02P9/08 ,  H02P9/30 ,  H02P9/00

CPC classification number: H02P9/08 ,  H02P2101/45

Abstract: The contrasting requirements of low power consumption during operation and ability to function under drastic drops of the supply voltage at start-up of output power stages of an electric system of self-generation and recharge of a storage battery, are satisfied by an output power driving stage composed of a bipolar transistor and a field effect transistor, functionally connected in parallel to each other and having independent control terminals. A control signal is selectably switched either to the base of the bipolar output transistor or to the gate of the field effect output transistor, depending on the level of the supply voltage. A comparator comparing the voltage present on the supply node with a reference voltage controls a selection switch. The low threshold of the bipolar transistor ensures functioning at start-up, while the field effect transistor provides a low power consumption during normal running conditions.

Abstract translation: 通过输出功率驱动来满足运行中的低功耗和在蓄电池的自发电和再充电的输出功率级的启动时的电源电压急剧下降下的功能的对比要求 由双极晶体管和场效应晶体管组成的级，彼此并联并具有独立的控制端子。 取决于电源电压的电平，控制信号可选地切换到双极性输出晶体管的基极或者到场效应输出晶体管的栅极。 比较供电节点上存在的电压与参考电压的比较器控制选择开关。 双极晶体管的低阈值确保启动时的功能，而场效应晶体管在正常运行条件下提供低功耗。

公开(公告)号：US5535157A

公开(公告)日：1996-07-09

申请号：US347653

申请日：1994-11-30

Applicant: Giovanni Campardo ,  Raffaele Costa ,  Piero Torricelli

Inventor： Giovanni Campardo ,  Raffaele Costa ,  Piero Torricelli

IPC: G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16 ,  G11C16/22 ,  G11C7/00

CPC classification number: G11C16/0416 ,  G11C16/04 ,  G11C16/16 ,  G11C16/22

Abstract: An integrated device with electrically programmable and erasable memory cells, including one time programmable (OTP) read-only memory cells. A matrix of user memory cells is added at least one row of OTP cells sharing the column selection lines with the other cells. Similarly to the other cells, these have a selection terminal connected to a row selection line. The source terminals of such OTP cells in the row are connected to the device ground through a common selection transistor which is driven from the same row selection line.

Abstract translation: 具有电可编程和可擦除存储单元的集成器件，包括一次可编程（OTP）只读存储器单元。 将用户存储单元的矩阵添加到与其他单元共享列选择行的至少一行OTP单元。 与其他单元类似，它们具有连接到行选择线的选择端子。 该行中的这种OTP单元的源极端子通过从相同行选择线驱动的公共选择晶体管连接到器件地。

公开(公告)号：US5534813A

公开(公告)日：1996-07-09

申请号：US201208

申请日：1994-02-24

Applicant: Marco DeMicheli

Inventor： Marco DeMicheli

IPC: G06G7/24 ,  H03F1/30 ,  H03F3/45 ,  H03G7/00 ,  G06F7/556 ,  G06G7/20

CPC classification number: H03G7/001 ,  G06G7/24

Abstract: An anti-logarithmic type converter circuit, with temperature compensation, includes a diode connected between a unity gain, non-inverting interface circuit and a low-impedance reference voltage circuit. A thermal compensation circuit is connected between the converter input and the interface circuit. The thermal compensation circuit includes current mirror circuits having a gain higher than one and their output currents linearly dependent on temperature.

Abstract translation: 具有温度补偿的反对数型转换器电路包括连接在单位增益，非反相接口电路和低阻参考电压电路之间的二极管。 转换器输入和接口电路之间连接一个热补偿电路。 热补偿电路包括具有高于1的增益的电流镜电路，并且其输出电流线性地依赖于温度。