公开(公告)号：US20190123202A1

公开(公告)日：2019-04-25

申请号：US16226875

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L29/06 ,  H01L29/51

CPC classification number: H01L29/7851 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-κ dielectric layer and a gate electrode. The high-κ dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-κ dielectric layer.

公开(公告)号：US10157795B2

公开(公告)日：2018-12-18

申请号：US15727626

申请日：2017-10-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Wei-Ting Chen

IPC: H01L27/088 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/12 ,  H01L21/84

Abstract: A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The first gate is disposed over the first fin. The second gate is disposed over the second fin. A gap is formed between the first gate and the second gate, and the gap gets wider toward the substrate. The insulating structure is disposed in the gap. The insulating structure has a top surface and a bottom surface opposite to each other. The bottom surface faces the substrate. An edge of the top surface facing the first gate is curved inward the top surface.

公开(公告)号：US20180350970A1

公开(公告)日：2018-12-06

申请号：US16043111

申请日：2018-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/66 ,  H01L23/535 ,  H01L29/417 ,  H01L21/308

CPC classification number: H01L29/785 ,  H01L21/3085 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/6656 ,  H01L29/66795

Abstract: Contact structures, FinFET devices and methods of forming the same are disclosed. One of the contact structures includes a source/drain region, a mask layer, a connector and a shielding pattern. The source/drain region is between two gate stacks. A mask layer is over the gate stacks and has an opening corresponding to the source/drain region. The connector is electrically connected to the source/drain region, penetrates through the opening of the mask layer and protrudes above and below the mask layer. The shielding pattern is between the mask layer and the connector and in physical contact with the mask layer.

公开(公告)号：US10147821B2

公开(公告)日：2018-12-04

申请号：US15715153

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

公开(公告)号：US20180337279A1

公开(公告)日：2018-11-22

申请号：US16050703

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng CHANG ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/06 ,  H01L21/283

Abstract: A FinFET device structure and method for forming the same are provided. The Fin PET device structure includes a stop layer formed over a substrate and a fin structure formed over the stop layer. The FinFET device structure includes a gate structure formed over the fin structure and a source/drain (S/D) structure adjacent to the gate structure. A bottom surface of the S/D structure is located at a position that is higher than or level with a bottom surface of the stop layer.

公开(公告)号：US10090249B2

公开(公告)日：2018-10-02

申请号：US15016144

申请日：2016-02-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/8238 ,  H01L23/535 ,  H01L29/08 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source drain structure, a first dielectric layer, a conductor, and a protection layer. The first gate structure is present on the substrate. The first spacer is present on a sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The first dielectric layer is present on the first gate structure and has an opening therein, in which the source drain structure is exposed through the opening. The conductor is electrically connected to the source drain structure, in which the conductor has an upper portion in the opening of the first dielectric layer and a lower portion between the upper portion and the source drain structure. The protection layer is present between the lower portion and the first spacer and between the upper portion and the source drain structure.

公开(公告)号：US10084085B2

公开(公告)日：2018-09-25

申请号：US14792303

申请日：2015-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/283 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a stop layer formed over a substrate and a fin structure formed over the stop layer. The FinFET device structure includes a gate structure formed over the fin structure and a source/drain (S/D) structure adjacent to the gate structure. A bottom surface of the S/D structure is located at a position that is higher than or level with a bottom surface of the stop layer.

公开(公告)号：US10032913B2

公开(公告)日：2018-07-24

申请号：US14990797

申请日：2016-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/28 ,  H01L21/768 ,  H01L21/308 ,  H01L23/535 ,  H01L29/417 ,  H01L29/66

Abstract: Contact structures, FinFET devices and methods of forming the same are disclosed. One of the contact structures includes a source/drain region, a mask layer, a connector and a shielding pattern. The source/drain region is between two gate stacks. A mask layer is over the gate stacks and has an opening corresponding to the source/drain region. The connector is electrically connected to the source/drain region, penetrates through the opening of the mask layer and protrudes above and below the mask layer. The shielding pattern is between the mask layer and the connector and in physical contact with the mask layer.

公开(公告)号：US09991256B2

公开(公告)日：2018-06-05

申请号：US14968468

申请日：2015-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Po-Chi Wu ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/66545

Abstract: A method for manufacturing a semiconductor structure includes forming a plurality of dummy semiconductor fins on a substrate. The dummy semiconductor fins are adjacent to each other and are grouped into a plurality of fin groups. The dummy semiconductor fins of the fin groups are recessed one group at a time.

公开(公告)号：US09893060B2

公开(公告)日：2018-02-13

申请号：US14987294

申请日：2016-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L21/28114 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a core device, and an input/output (I/O) device. The core device is disposed on the substrate. The core device includes a first gate electrode having a bottom surface and at least one sidewall. The bottom surface of the first gate electrode and the sidewall of the first gate electrode intersect to form a first interior angle. The I/O device is disposed on the substrate. The I/O device includes a second gate electrode having a bottom surface and at least one sidewall. The bottom surface of the second gate electrode and the sidewall of the second gate electrode intersect to form a second interior angle greater than the first interior angle of the first gate electrode.