公开(公告)号：US11687281B2

公开(公告)日：2023-06-27

申请号：US17219535

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

Abstract: A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. The arbiter transacts a streak for at least a minimum burst length based on a number of commands of a designated type available to be selected by the arbiter. Following the minimum burst length, the arbiter decides to start a new streak of commands of a different type based on a first set of one or more conditions indicating intra-burst efficiency.

公开(公告)号：US20230198772A1

公开(公告)日：2023-06-22

申请号：US17555020

申请日：2021-12-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Andrew G. Kegel

IPC: H04L9/32 ,  G06N3/08

CPC classification number: H04L9/3239 ,  G06N3/08

Abstract: An approach is provided for implementing a useful proof-of-work consensus algorithm. A proposed block is received. A combined hash value is generated based on the proposed block and a nonce value. The combined hash value is divided into a plurality of hash value pieces that each correspond to a work packet of a plurality of work packets. One or more requests are transmitted for the plurality of work packets that correspond to the plurality of hash value pieces. In response to receiving the plurality of work packets, a plurality of results is generated by performing, for each work packet of the plurality of work packets, one or more operations to complete work specified by the respective work packet. In response to determining that at least one result of the plurality of results satisfies one or more criteria, the proposed block is added to a blockchain maintained by the blockchain network.

公开(公告)号：US20230198207A1

公开(公告)日：2023-06-22

申请号：US17554868

申请日：2021-12-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Lin Wang ,  Yuyang Jiang ,  Xiaohua Wang ,  Kaichun Ning

IPC: H01R13/648

CPC classification number: H01R13/6485

Abstract: A system and method for efficient methods and systems for input/output port protection from electrostatic discharge events are described. In various implementations, an integrated circuit mounted on a printed circuit board includes a connector port that uses a first signal pin within a metal shell mounted on the printed circuit board and is electrically connected to a ground reference. The first signal pin is electrically connected to the ground reference though a spring pin located between itself and the shell. A user inserts a head contact of a cable into the connector port. The head contact includes a second signal pin that is floating, but becomes connected to the ground reference when brought into physical contact with the first signal pin. During later insertion, the head contact pushes the spring pin causing physical disconnection of the spring pin from the first signal pin allowing data transmission to begin.

公开(公告)号：US20230197619A1

公开(公告)日：2023-06-22

申请号：US17556346

申请日：2021-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gabriel H LOH ,  Raja Swaminathan ,  Rahul Agarwal ,  Brett P. Wilkerson

IPC: H01L23/538 ,  G05F1/575 ,  H01L25/065 ,  H01L27/06

CPC classification number: H01L23/5384 ,  G05F1/575 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0657 ,  H01L27/0688

Abstract: A semiconductor package includes a package substrate having a first surface and an opposing second surface, and further includes an integrated circuit (IC) die disposed at the second surface and having a third surface facing the second surface and an opposing fourth surface. The IC die has a first region comprising one or more metal layers and circuit components for one or more functions of the IC die and a second region offset from the first region in a direction parallel with the third and fourth surfaces. The semiconductor package further includes a voltage regulator disposed at the fourth surface in the second region and having an input configured to receive a supply voltage and an output configured to provide a regulated voltage, and also includes a conductive path coupling the output of the voltage regulator to a voltage input of circuitry of the IC die.

公开(公告)号：US20230195992A1

公开(公告)日：2023-06-22

申请号：US17558472

申请日：2021-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Wilson Li ,  Roydan N. Ongie ,  Mackenzie Peterson

IPC: G06F30/398 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392

Abstract: A method for handling engineering change orders (ECOs) for an integrated circuit design is described herein. An ECO program performs operations for an ECO flow. The ECO flow includes the ECO program generating a changed design by applying ECO changes for a set of ECOs to integrated circuits in an initial design. The ECO program then finds ECO change rule violations for the changed design. The ECO program next identifies selected ECOs associated with ECO change rule violations. The ECO program then removes the selected ECOs from the set of ECOs.

公开(公告)号：US20230195645A1

公开(公告)日：2023-06-22

申请号：US17556431

申请日：2021-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SOORAJ PUTHOOR ,  MUHAMMAD AMBER HASSAAN ,  ASHWIN AJI ,  MICHAEL L. CHU ,  NUWAN JAYASENA

IPC: G06F12/1009 ,  G06F12/1045 ,  G06F12/02 ,  G06F13/16

CPC classification number: G06F12/1009 ,  G06F12/1054 ,  G06F12/1063 ,  G06F12/0238 ,  G06F13/1673 ,  G06F2212/7201

Abstract: Process isolation for a PIM device includes: receiving, from a process, a call to allocate a virtual address space where the process stores a PIM configuration context; allocating the virtual address space including mapping a physical address space including PIM device configuration registers to the virtual address space only if the physical address space is not mapped to another process's virtual address space; and programming the PIM device configuration space according to the configuration context. When a PIM command is executed, a translation mechanism determines whether there is a valid mapping of a virtual address of the PIM command to a physical address of a PIM resource, such as a LIS entry. If a valid mapping exists, the translation is completed and the resource is accessed, but if there is not a valid mapping, the translation fails and the process is blocked from accessing the PIM resource.

公开(公告)号：US20230195628A1

公开(公告)日：2023-06-22

申请号：US17558034

申请日：2021-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Akhil Arunkumar ,  Tarun Nakra ,  Maxim V. Kazakov ,  Milind N. Nemlekar

IPC: G06F12/0811 ,  G06F12/0853 ,  G06F13/16

CPC classification number: G06F12/0811 ,  G06F12/0853 ,  G06F13/1642 ,  G06F13/1668

Abstract: Methods, systems, and devices maintain state information in a shadow tag memory for a plurality of cachelines in each of a plurality of private caches, with each of the private caches being associated with a corresponding one of multiple processing cores. One or more cache probes are generated based on a write operation associated with one or more cachelines of the plurality of cachelines, such that each of the cache probes is associated with cachelines of a particular private cache of the multiple private caches, the particular private cache being associated with an indicated processing core. Transmission of the cache probes to the particular private cache is prevented until, responsive to a scope acquire operation from the indicated processing core, the cache probes are released for transmission to the respectively associated cachelines in the particular private cache.

公开(公告)号：US11681620B2

公开(公告)日：2023-06-20

申请号：US17384420

申请日：2021-07-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Marko Scrbak ,  Jagadish Kotra

IPC: G06F12/0808 ,  G06F11/10

CPC classification number: G06F12/0808 ,  G06F11/1064 ,  G06F2212/1044

Abstract: An electronic device includes a cache memory and a controller. The cache memory includes a set of cache blocks, each cache block having a number of locations usable for storing cache lines. The cache memory also includes a separate set of error correction code (ECC) bits for each of the locations. The controller stores a victim cache line, evicted from a first location in the cache block, in a second location in the cache block. The controller next stores victim reference information in a portion of the plurality of ECC bits for the first location, the victim reference information indicating that the victim cache line is stored in the second location.

公开(公告)号：US20230188336A1

公开(公告)日：2023-06-15

申请号：US17547866

申请日：2021-12-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Donald Preston Matthews, JR.

IPC: H04L9/08 ,  H04L9/14

CPC classification number: H04L9/0861 ,  H04L63/0428 ,  H04L9/14 ,  H04L9/0822

Abstract: Automatic key rolling for link encryption is described. In accordance with the described techniques, data packets are encrypted at a first endpoint of a communication link using a first data encryption key. The encrypted data packets are communicated over the communication link to a second endpoint. A key rolling event that is known by both the first endpoint and the second endpoint is detected at the first endpoint. Responsive to detecting the key rolling event, the first data encryption key is rolled to a second data encryption key for encrypting data packets communicated over the communication link. In one or more implementations, the second endpoint is also configured to roll from the first data encryption key to the second data encryption key responsive to the key rolling event in order to decrypt data packets encrypted with the second data encryption key which are received from the first endpoint.

公开(公告)号：US20230187364A1

公开(公告)日：2023-06-15

申请号：US17644191

申请日：2021-12-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Chia-Hao Cheng ,  Kong Toon Ng ,  Rahul Agarwal ,  Brett P. Wilkerson

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5384 ,  H01L21/486

Abstract: An embodiment of a semiconductor chip device can include a molding layer having a first side and a second side, an interconnect chip at least partially encased in the molding layer, the interconnect chip comprising a through substrate via (TSV) that extends through the interconnect chip, an insulating layer positioned on the first side of the molding layer, and a conductive structure that is positioned vertically below the interconnect chip and extends through the insulating layer, wherein the conductive structure is electrically coupled to the TSV.