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公开(公告)号:US20210305290A1
公开(公告)日:2021-09-30
申请号:US16829553
申请日:2020-03-25
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Yusheng Bian , Michel Rakowski , Won Suk Lee , Asif Chowdhury , Ajey Poovannummoottil Jacob
IPC: H01L27/146 , H01L31/0232 , H01L31/101
Abstract: Structures for a photodetector and methods of fabricating a structure for a photodetector. The structure includes a light-absorbing region having a side edge, an anode adjacent to the side edge of the light-absorbing region, and a cathode adjacent to the side edge of the light-absorbing region.
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公开(公告)号:US20210305103A1
公开(公告)日:2021-09-30
申请号:US16828273
申请日:2020-03-24
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Sipeng Gu , Judson Holt , Haiting Wang , Bangun Indajang
IPC: H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/10
Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. First and second gate structures extend over the semiconductor body. A source/drain region is positioned laterally between the first gate structure and the second gate structure. The source/drain region includes a semiconductor layer having a first section, a second section, and a third section. A first portion of the semiconductor body is positioned between the first section of the semiconductor layer and the second section of the semiconductor layer. A second portion of the semiconductor body is positioned between the second section of the semiconductor layer and the third section of the semiconductor layer.
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公开(公告)号:US20210302651A1
公开(公告)日:2021-09-30
申请号:US16836047
申请日:2020-03-31
Inventor: Yusheng Bian , Sujith Chandran , Jaime Viegas , Humarira Zafar , Ajey Poovannummoottil Jacob
Abstract: Structures for a polarizer and methods of fabricating a structure for a polarizer. A waveguide crossing includes a first arm and a second arm. A waveguide loop couples the first arm of the waveguide crossing to the second arm of the waveguide crossing. The waveguide crossing and the waveguide loop provide a structure for the polarizer.
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公开(公告)号:US11127818B2
公开(公告)日:2021-09-21
申请号:US16526529
申请日:2019-07-30
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Jagar Singh , Srikanth Balaji Samavedam
IPC: H01L29/08 , H01L21/8234 , H01L29/423 , H01L27/088
Abstract: An illustrative device includes a transistor including a first set of fins defined above a substrate, a second set of fins defined above the substrate, and a gate structure embedded in the substrate between the first set of fins and the second set of fins, wherein the first set of fins and the second set of fins are doped with a first dopant type and the substrate is doped with a second dopant type different than the first dopant type.
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公开(公告)号:US11127816B2
公开(公告)日:2021-09-21
申请号:US16791214
申请日:2020-02-14
Applicant: GLOBALFOUNDRIES U.S. INC.
Inventor: Siva P. Adusumilli , Rajendran Krishnasamy , Steven M. Shank , Vibhor Jain
IPC: H01L29/08 , H01L29/49 , H01L29/16 , H01L29/737 , H01L29/66
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having one or more sealed airgap and methods of manufacture. The structure includes: a subcollector region in a substrate; a collector region above the substrate; a sealed airgap formed at least partly in the collector region; a base region adjacent to the collector region; and an emitter region adjacent to the base region.
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公开(公告)号:US20210288182A1
公开(公告)日:2021-09-16
申请号:US16819832
申请日:2020-03-16
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Sipeng Gu , Judson Holt , Haiting Wang
Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. First and second gate structures extend over the semiconductor body, a second gate structure that extends over the semiconductor body. A source/drain region is positioned laterally between the first gate structure and the second gate structure. The source/drain region includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer has a first section and a second section. The second semiconductor layer is positioned laterally between the first section of the first semiconductor layer and the second section of the first semiconductor layer.
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公开(公告)号:US11121087B2
公开(公告)日:2021-09-14
申请号:US16726447
申请日:2019-12-24
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Nicholas LiCausi , Julien Frougier , Keith Donegan , Hyung Woo Kim
IPC: H01L23/522 , H01L23/532 , H01L21/768 , H01L23/528 , G11C5/06
Abstract: One illustrative device disclosed herein includes a layer of insulating material having an upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein the recessed conductive interconnect structure has a recessed upper surface that is positioned at a second level that is below the first level. In this example, the device also includes a recess defined in the recessed conductive interconnect structure, a memory cell positioned above the recessed conductive interconnect structure and a conductive via plug that is conductively coupled to the recessed conductive interconnect structure and a lower conductive material of the memory cell, wherein at least a portion of the conductive via plug is positioned in the recess defined in the recessed conductive interconnect.
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公开(公告)号:US11120857B2
公开(公告)日:2021-09-14
申请号:US16720058
申请日:2019-12-19
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Akhilesh Jaiswal , Bipul C. Paul
Abstract: Disclosed is a reference circuit having an even number m of groups of m parallel-connected magnetic tunnel junctions (MTJs). The MTJs in half of the groups are programmed to have parallel resistances (RP) and the MTJs in the other half are programmed to have anti-parallel resistances (RAP). Switches connect the groups in series, creating a series-parallel resistor network. The total resistance (RT) of the network has low variability and is essentially equal to half the sum of a nominal RP plus a nominal RAP and can be employed as a reference resistance (RREF). Under specific biasing conditions the series-parallel resistor network can generate a low variability reference parameter (XREF) that is dependent on this RREF. Also disclosed are an integrated circuit (IC) that includes the reference circuit and a magnetic random access memory (MRAM) structure, which uses XREF to determine stored data values in MRAM cells and associated methods.
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公开(公告)号:US20210280703A1
公开(公告)日:2021-09-09
申请号:US16807623
申请日:2020-03-03
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Bartlomiej J. Pawlak , Dimitri Lederer
IPC: H01L29/778 , H01L29/15 , H01L29/16 , H01L29/20 , H01L29/205 , H01L29/66 , H01L21/02
Abstract: Structures including a buffer layer and methods of forming a structure including a buffer layer. A layer stack is formed on a semiconductor substrate. The layer stack includes a buffer layer and a charge-trapping layer. The buffer layer is composed of a III-V compound semiconductor material, and the charge-trapping layer is positioned between the semiconductor substrate and the buffer layer.
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公开(公告)号:US20210278742A1
公开(公告)日:2021-09-09
申请号:US16808613
申请日:2020-03-04
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Yusheng Bian , Ajey Poovannummoottil Jacob
IPC: G02F1/313
Abstract: One illustrative device disclosed herein includes a lower waveguide structure and an upper body structure positioned above at least a portion of the lower waveguide structure. In this example, the device also includes a grating structure positioned in the upper body structure, wherein the grating structure comprises a plurality of grating elements that comprise a tunable material whose index of refraction may be changed by application of energy to the tunable material.
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