公开(公告)号：US20190094296A1

公开(公告)日：2019-03-28

申请号：US15713168

申请日：2017-09-22

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: G01R31/28

CPC classification number: G01R31/2896 ,  G01R31/2856 ,  G01R31/2886 ,  H03K19/20

Abstract: Disclosed herein is circuitry for bypassing a medium voltage regulator during testing. The circuitry includes a low voltage regulator to, in operation, generate a first voltage within a first voltage range for powering first circuitry, and a medium voltage regulator to, in operation, generate a second voltage within a second voltage range greater than the first voltage range for powering second circuitry. A low voltage regulator bypass circuit generates a low voltage regulator bypass signal that operates to selectively bypass the low voltage regulator. A medium voltage regulator bypass circuit bypasses the medium voltage regulator as a function of the low voltage regulator bypass signal and an external voltage regulator select signal, the bypass of the medium voltage regulator being such that an external voltage can be applied to the second circuitry.

公开(公告)号：US20190086474A1

公开(公告)日：2019-03-21

申请号：US15710172

申请日：2017-09-20

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: G01R31/327 ,  H03K19/20

Abstract: A method of operating an electronic device during test mode operation of a duplicated voltage monitor includes sensing a functional supply voltage with a voltage monitor, deasserting an output of the voltage monitor if the functional supply voltage is exceeds a threshold, and asserting output of the voltage monitor if the functional supply voltage falls below the threshold. A test supply voltage is sensed with the duplicate voltage monitor, output of the duplicate voltage monitor is deasserted if the test supply voltage exceeds a threshold, and output of the duplicate voltage monitor is asserted if the test supply voltage falls below the threshold. Output of the duplicate voltage monitor is monitored to thereby determine the threshold based upon assertion of the output of the duplicate voltage monitor, and performing a logical operation between outputs of the voltage monitor and the duplicate voltage monitor to generate a power on reset signal.

公开(公告)号：US10228420B2

公开(公告)日：2019-03-12

申请号：US15268848

申请日：2016-09-19

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Nimit Endlay ,  Balwinder Singh Soni

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3193 ,  G06F11/26 ,  G06F11/25 ,  G06F11/27

Abstract: A test circuit receives LBIST and ATPG mode signals, and generates a first output as high when in ATPG or LBIST, and a second output as low when in ATPG or LBIST. A multiplexing circuit receives an ATPG clock and functional clock, and outputs one. A clock gate circuit includes a first latch receiving the second output, and an enable input receiving an inverse of the ATPG clock or functional clock. A second latch receives the first output, and has an enable input receiving the inverse of the ATPG clock or functional clock. The clock gate circuit includes a first AND gate receiving output of the first latch and ATPG clock or functional clock, a second AND gate receiving output of the second latch and the ATPG clock or LBIST clock, and an OR gate receiving outputs of the first and second AND gates, and generating a test clock.

公开(公告)号：US10211727B1

公开(公告)日：2019-02-19

申请号：US16028814

申请日：2018-07-06

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: H02M3/18 ,  H02M3/07 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092

Abstract: A voltage multiplier circuit operates in response to a received clock signal to perform a voltage multiplication operation on an input voltage to generate an output voltage. The voltage multiplier circuit includes a pair of intermediate nodes that are capacitively coupled to receive, respectively, opposite phases of a clock signal. A first CMOS driver circuit is coupled to one of the intermediate nodes and has an output configured to generate one phase of a level shifted output clock signal. A second CMOS driver circuit is coupled to another one of the intermediate nodes and has an output configured to generate another phase of the level shifted output clock signal.

公开(公告)号：US20190036568A1

公开(公告)日：2019-01-31

申请号：US15757771

申请日：2016-09-21

Applicant: STMicroelectronics International N.V.

Inventor： Kosta Kovacic ,  Albin Pevec

IPC: H04B5/00 ,  H04W4/80 ,  H04L27/04 ,  H04B1/04 ,  G06K7/10

CPC classification number: H04B5/0062 ,  G06K7/10366 ,  H04B1/04 ,  H04B5/0031 ,  H04L27/04 ,  H04W4/80

Abstract: When communicating using active load modulation in a Radio Frequency Identification (RFID) system, a carrier signal having a carrier frequency is received from a reader device. In response, a modulated signal is generated and a burst of a sending signal is transmitted. The sending signal is decayed at the end of the burst.

公开(公告)号：US10180324B2

公开(公告)日：2019-01-15

申请号：US15197414

申请日：2016-06-29

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS, INC. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Carlo Valzasina ,  Huantong Zhang ,  Matteo Fabio Brunetto ,  Gert Ingvar Andersson ,  Erik Daniel Svensson ,  Nils Einar Hedenstierna

IPC: G01C19/56 ,  G01P9/04 ,  G01C19/574 ,  G01C19/5719 ,  G01C19/5776

Abstract: A gyroscope includes a substrate, a first structure, a second structure and a third structure elastically coupled to the substrate and movable along a first axis. The first and second structure are arranged at opposite sides of the third structure with respect to the first axis A driving system is configured to oscillate the first and second structure along the first axis in phase with one another and in phase opposition with the third structure. The first, second and third structure are provided with respective sets of sensing electrodes, configured to be displaced along a second axis perpendicular to the first axis in response to rotations of the substrate about a third axis perpendicular to the first axis and to the second axis.

公开(公告)号：US20180343152A1

公开(公告)日：2018-11-29

申请号：US15580843

申请日：2016-06-09

Applicant: STMicroelectronics International N.V.

Inventor： Vinko Kunc ,  Albin Pevec ,  Kosta Kovacic

IPC: H04L27/06 ,  H03D1/18 ,  H03D1/22 ,  H03D1/02 ,  H04L27/26

Abstract: A demodulator circuit receives an envelope signal for comparison against a switched reference signal that is generated as a function of the envelope signal and as a function of an output signal of the demodulator circuit. The switched reference signal is filtered by an RC filter prior to comparison. The output signal is dependent on a difference between the filtered switched reference signal and the envelope signal.

公开(公告)号：US10127990B1

公开(公告)日：2018-11-13

申请号：US15652564

申请日：2017-07-18

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: G11C16/06 ,  G11C16/28 ,  G11C16/14 ,  G11C16/08

Abstract: A memory array includes rows and columns with memory cell portion and a dummy cell portion. Bit lines are connected to the memory cells and to the dummy cell portion. The dummy cell portion includes a first row of dummy cells and a second row of dummy cells. The dummy cells in the first row have a first connection to a corresponding bit line of a first bit line group of the bit lines and a second connection to a first source line. The dummy cells in the second row have a first connection to a corresponding bit line of a second bit line group of the plurality of bit lines and a second connection to a second source line. The dummy cells are selectively actuated to couple voltages at the first and second source lines to the first and second bit line groups, respectively, depending on memory operating mode.

公开(公告)号：US20180320650A1

公开(公告)日：2018-11-08

申请号：US16036737

申请日：2018-07-16

Applicant: STMicroelectronics International N.V.

Inventor： Laurent Perier

IPC: F02N11/04 ,  H02P9/00

CPC classification number: F02N11/04 ,  F02B61/02 ,  F02N2011/0896 ,  F02N2200/0801 ,  F02N2200/101 ,  F02N2200/102 ,  F02N2200/103 ,  H02K11/048 ,  H02P9/00 ,  H02P9/48

Abstract: A method and system of improving the efficiency of motor vehicles includes stopping an engine of a motor vehicle system if the motor vehicle system is immobile for more than a predetermined period of time, according to one embodiment. The method and system includes starting the engine with a magneto system, in response to one or more vehicle conditions, such as operation of a throttle, operation of a clutch, and/or operation of a brake lever, according to one embodiment.

公开(公告)号：US20180287620A1

公开(公告)日：2018-10-04

申请号：US15471483

申请日：2017-03-28

Applicant: STMicroelectronics International N.V.

Inventor： Gagan Midha ,  Kallol Chatterjee

IPC: H03L7/093 ,  H03M3/00 ,  H03L7/081 ,  H03L7/08

Abstract: A phase locked loop (PLL) circuit disclosed herein includes a phase detector receiving a reference frequency signal and a feedback frequency signal, and configured to output a digital signal indicative of a phase difference between the reference frequency signal and the feedback frequency signal. A digital loop filter filters the digital signal. A digital to analog converter converts the filtered digital signal to a control signal. An oscillator generates a PLL clock signal based on the control signal. A sigma-delta modulator modulates a divider signal as a function of a frequency control word. A divider divides the PLL clock signal based on the divider signal, and generates a noisy feedback frequency signal based thereupon. A noise filtering block removes quantization noise from the noisy feedback frequency signal to thereby generate the feedback frequency signal.