公开(公告)号：US11621271B2

公开(公告)日：2023-04-04

申请号：US17177164

申请日：2021-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu

IPC: H01L21/28 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US20230101900A1

公开(公告)日：2023-03-30

申请号：US18077191

申请日：2022-12-07

Applicant: United Microelectronics Corp.

Inventor： Zhirui Sheng ,  Hui-Ling Chen ,  Chung-Hsing Kuo ,  Chun-Ting Yeh ,  Ming-Tse Lin ,  Chien En Hsu

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/66

Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

公开(公告)号：US20230099443A1

公开(公告)日：2023-03-30

申请号：US17505663

申请日：2021-10-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hon-Huei Liu ,  Shih-Hung Tsai ,  Chun-Hsien Lin

IPC: H01L27/11507

Abstract: The invention provides a semiconductor structure, which comprises a substrate with at least a first transistor and a second transistor, and a capacitor structure in a dielectric layer above the substrate, wherein the capacitor structure is electrically connected with a gate of the first transistor and a drain of the second transistor.

公开(公告)号：US20230094739A1

公开(公告)日：2023-03-30

申请号：US17510392

申请日：2021-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： CHUNYUAN QI ,  Sheng Zhang ,  XINGXING CHEN ,  Chien-Kee Pang

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/16

Abstract: An silicon-on-insulator substrate is provided in the present invention, including a handler, a polysilicon trap-rich layer formed on the handler, an oxide layer formed on the polysilicon trap-rich layer and a monocrystalline silicon layer formed directly on the oxide layer, wherein a bonding interface is between the monocrystalline silicon layer and the oxide layer.

公开(公告)号：US11616139B2

公开(公告)日：2023-03-28

申请号：US17224108

申请日：2021-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yen Feng ,  Chen-An Kuo ,  Ching-Wei Teng ,  Po-Chun Lai

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/285 ,  H01L21/74 ,  H01L29/45

Abstract: An LDMOS includes a semiconductor substrate. A well is disposed within the semiconductor substrate. A body region is disposed within the well. A first gate electrode is disposed on the semiconductor substrate. A source electrode is disposed at one side of the first gate electrode. The source electrode includes a source contact area and numerous vias. The vias connect to the source contact area. The vias extend into the semiconductor substrate. A first drain electrode is disposed at another side of the first gate electrode and is opposed to the source electrode.

公开(公告)号：US20230091364A1

公开(公告)日：2023-03-23

申请号：US18073574

申请日：2022-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Chen ,  Hui-Lin Wang ,  Yu-Ru Yang ,  Chin-Fu Lin ,  Yi-Syun Chou ,  Chun-Yao Yang

IPC: H01L27/22 ,  H01L23/552 ,  H01L43/10 ,  H01F41/34 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

公开(公告)号：US11611035B2

公开(公告)日：2023-03-21

申请号：US17182146

申请日：2021-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Jian-Cheng Chen ,  Yu-Ping Wang ,  Yu-Ruei Chen

IPC: H01L27/22 ,  H01L43/02 ,  G11C11/16 ,  H01L27/02

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

公开(公告)号：US11610973B2

公开(公告)日：2023-03-21

申请号：US17564104

申请日：2021-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Kai-Lin Lee ,  Wei-Jen Chen

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66

Abstract: A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. A gate dielectric layer is disposed under the metal compound layer and contacts the substrate.

公开(公告)号：US20230079155A1

公开(公告)日：2023-03-16

申请号：US17990749

申请日：2022-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/423 ,  H01L29/786 ,  H01L27/092

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first transistor is formed on a substrate. The first transistor includes a first semiconductor channel structure and two first source/drain structures. The first semiconductor channel structure includes first horizontal portions and a first vertical portion. The first horizontal portions are stacked in a vertical direction and separated from one another. Each of the first horizontal portions is elongated in a horizontal direction. The first vertical portion is elongated in the vertical direction and connected with the first horizontal portions. The two first source/drain structures are disposed at two opposite sides of each of the first horizontal portions in the horizontal direction respectively. The two first source/drain structures are connected with the first horizontal portions.

公开(公告)号：US20230073022A1

公开(公告)日：2023-03-09

申请号：US17987867

申请日：2022-11-16

Applicant: United Microelectronics Corp.

Inventor： Nuo Wei Luo ,  Huabiao Wu

IPC: H01L21/68 ,  H01L21/027 ,  G03F7/20 ,  H01L23/544

Abstract: Provided is a semiconductor device includes a substrate, an isolation structure, an alignment mark, and a dielectric layer. The substrate includes a first region and a second region. The isolation structure is disposed in the substrate in the first region, wherein the isolation structure extends from a first surface of the substrate toward a second surface of the substrate.
The alignment mark is disposed in the substrate in the second region. The alignment mark extends from the first surface of the substrate toward the second surface of the substrate and at the same level as the isolation structure. The dielectric layer is buried in the substrate in the second region and overlapping the alignment mark.