-
公开(公告)号：US09558052B2
公开(公告)日：2017-01-31
申请号：US14218482
申请日：2014-03-18
Inventor： Om Ranjan , Giampiero Borgonovo , Deepak Baranwal
CPC classification number: G06F11/0736 , G05B19/0428 , G05B23/0254 , G05B2219/2637 , G06F11/2205 , G06F11/3013
Abstract: A safety system monitors faults in an embedded control system. The embedded control system is modeled to produce one or more model check values by calculating how many clock cycles will pass between an initialization time point and at least one event time point for a specific event. The initialization time point is a certain point in an initialization function of a scheduler in the embedded control system. The at least one event time point is an expected number of clock cycles to pass before a specific event occurs. In operation, the embedded control system is initialized, a current clock cycle counter value is retrieved at a certain point in the initialization, and either an occurrence or an absence of an occurrence of a scheduled event is recognized. A current clock cycle value is recorded upon the recognition, and a mathematic check value is produced from the clock cycle value stored at the certain point in the initialization and the clock cycle value recorded upon the recognition. Subsequently, the model check value is compared to the mathematic check value, and action is taken based on the comparison.
Abstract translation: 安全系统监控嵌入式控制系统中的故障。 嵌入式控制系统被建模为通过计算在特定事件的初始化时间点和至少一个事件时间点之间经过多少个时钟周期来产生一个或多个模型检查值。 初始化时间点是嵌入式控制系统中的调度器的初始化功能中的某一点。 至少一个事件时间点是在特定事件发生之前要通过的期望数量的时钟周期。 在操作中，初始化嵌入式控制系统，在初始化中的某一点检索当前的时钟周期计数器值，并且识别调度事件的发生或不存在。 在识别时记录当前时钟周期值，并且从存储在初始化中的某一点的时钟周期值和在识别时记录的时钟周期值产生数学校验值。 随后，将模型检查值与数学检查值进行比较，并根据比较进行动作。
-
公开(公告)号：US09524798B2
公开(公告)日：2016-12-20
申请号：US13960213
申请日：2013-08-06
Applicant: STMicroelectronics International N.V.
Inventor： Sajal Kumar Mandal
IPC: G11C27/02
CPC classification number: G11C27/026
Abstract: A circuit includes: a first circuit stage configured to sample a differential input signal at a first logic state of a sampling clock and regenerate the sampled differential input signal at a second logic state of the sampling clock to output a first regenerated differential signal; a second circuit stage configured to amplify the first regenerated differential signal at the second logic state of the sampling clock to output an amplified differential signal; and a third circuit stage configured to regenerate the amplified differential signal at the first logic state of the sampling clock to output a second regenerated differential signal.
Abstract translation: 电路包括：第一电路级，被配置为在采样时钟的第一逻辑状态下对差分输入信号进行采样，并在采样时钟的第二逻辑状态下重新产生采样的差分输入信号，以输出第一再生的差分信号; 第二电路级，被配置为在采样时钟的第二逻辑状态下放大第一再生差分信号，以输出放大的差分信号; 以及第三电路级，被配置为在采样时钟的第一逻辑状态下再生放大的差分信号，以输出第二再生的差分信号。
-
公开(公告)号：US09510195B2
公开(公告)日：2016-11-29
申请号：US14176832
申请日：2014-02-10
Applicant: STMicroelectronics International N.V.
Inventor： Laurent Perier
CPC classification number: H04W12/06 , H04L12/2825 , H04L63/0227 , H04L63/0428 , H04L63/123 , H04L63/1408 , H04W4/70 , H04W12/02
Abstract: A secure network enabled device has a distinct security module and lacks a human user input interface. The security module is formed in an integrated circuit. The security module is initialized. Data is electronically communicated to and from the secure network enabled device via at least one transceiver. The security module is configured to test the integrity of a subset of the data communicated to the secure network enabled device, and the security module is configured to test the integrity of a transaction protocol, which governs the stream of data bits of the data communicated to the secure network enabled device.
Abstract translation: 安全网络启用的设备具有不同的安全模块，并且缺少人类用户输入接口。 安全模块形成在集成电路中。 安全模块已初始化。 经由至少一个收发器将数据电子传送到和从启用安全网络的设备传送。 安全模块被配置为测试传送到启用安全网络的设备的数据的子集的完整性，并且安全模块被配置为测试事务协议的完整性，该事务协议控制传送到的数据的数据位流 安全网络启用设备。
-
公开(公告)号：US20160344395A1
公开(公告)日：2016-11-24
申请号：US15229322
申请日：2016-08-05
Applicant: STMicroelectronics International N.V.
Inventor： Abhirup Lahiri
CPC classification number: H03L7/0891 , H03L7/099
Abstract: Disclosed herein is a circuit including a phase frequency detector (PFD) configured to compare phases of an input signal and a feedback signal, and to generate first and second control signals as a function of that comparison. An attenuation circuit includes a capacitor coupled in series between a node and a switching node, and is configured to charge the capacitor and disconnect the switching node from ground based on assertion of the first control signal, and discharge the capacitor and connect the switching node to ground based on assertion of the second control signal.
Abstract translation: 这里公开了一种电路，其包括被配置为比较输入信号和反馈信号的相位的相位频率检测器（PFD），并且作为该比较的函数产生第一和第二控制信号。 衰减电路包括串联耦合在节点和开关节点之间的电容器，并且被配置为对电容器充电并且基于第一控制信号的断言将开关节点与地断开，并且将开关节点放电到 基于第二控制信号的断言接地。
-
公开(公告)号：US09473134B2
公开(公告)日：2016-10-18
申请号：US14166615
申请日：2014-01-28
Applicant: ST Microelectronics International N.V.
Inventor： Sameer Vashishtha
IPC: H03K3/00 , H03B1/00 , H03K17/687 , H03K19/0185 , H03K5/12
CPC classification number: H03K17/687 , H03K5/12 , H03K19/0185 , H03K19/018507
Abstract: A drive circuit includes an input, a driver, a first buffer, a second buffer, a first capacitance element, and a second capacitance element. The driver includes a first PMOS transistor and a first NMOS transistor coupled in series between a supply terminal and a reference terminal. The first buffer is coupled between the input and a control terminal of the first PMOS transistor. The second buffer is coupled between the input and a control terminal of the first NMOS transistor. The first capacitance element is coupled to the control terminal of the first PMOS transistor through a first semiconductor switch. The second capacitance element is coupled to the control terminal of the first NMOS transistor through a second semiconductor switch.
Abstract translation: 驱动电路包括输入，驱动器，第一缓冲器，第二缓冲器，第一电容元件和第二电容元件。 驱动器包括串联耦合在电源端子和参考端子之间的第一PMOS晶体管和第一NMOS晶体管。 第一缓冲器耦合在第一PMOS晶体管的输入端和控制端之间。 第二缓冲器耦合在第一NMOS晶体管的输入端和控制端之间。 第一电容元件通过第一半导体开关耦合到第一PMOS晶体管的控制端。 第二电容元件通过第二半导体开关耦合到第一NMOS晶体管的控制端子。
-
Patent Agency Ranking
公开(公告)号：US09467125B2
公开(公告)日：2016-10-11
申请号：US14573129
申请日：2014-12-17
Applicant: STMicroelectronics International N.V.
Inventor： Vinod Kumar , Saiyid Mohammad Irshad Rizvi
IPC: H03K3/3565
CPC classification number: H03K3/3565
Abstract: The Schmitt trigger circuit includes a signal input, a first inverter coupled to the signal input and configured to operate at a first voltage, and a second inverter coupled downstream of the first inverter and configured to operate at a second voltage lower than the first voltage. A protection device is coupled between the first inverter and the second inverter, and configured to limit a voltage input to the second inverter at the second voltage. A feedback circuit is coupled downstream of the protection device between the first inverter and the second inverter and configured to introduce hysteresis. An output circuit is coupled to the second inverter and configured to provide an output signal at the second voltage. The approach provides an architecture for 3.3V receivers designed by using 1.8V devices, without active power consumption from the I/O PAD during transition, and/or that supports CMOS standard levels for 1.8V and 3.3V receivers.
Abstract translation: 施密特触发电路包括信号输入端，耦合到信号输入并被配置为以第一电压工作的第一反相器，以及耦合在第一反相器下游的第二反相器，并被配置为在低于第一电压的第二电压下工作。 保护装置耦合在第一反相器和第二反相器之间，并且被配置为将第二反相器的电压输入限制在第二电压。 反馈电路被耦合在第一逆变器和第二逆变器之间的保护装置的下游，并被配置为引入滞后。 输出电路耦合到第二反相器并且被配置为提供处于第二电压的输出信号。 该方法为通过使用1.8V器件设计的3.3V接收器提供了架构，在转换期间没有来自I / O PAD的有功功耗，和/或支持1.8V和3.3V接收器的CMOS标准电平。
-
公开(公告)号：US09461584B2
公开(公告)日：2016-10-04
申请号：US14576535
申请日：2014-12-19
Applicant: STMicroelectronics International N.V.
Inventor： Gauri Mittal , Kallol Chatterjee , Pallavi Muktesh , Nitin Jain , Pradeep Kumar Badrathwal
IPC: H03B5/36
CPC classification number: H03B5/364 , H03B5/366 , H03B2200/0012 , H03B2200/0038
Abstract: A circuit includes an oscillator circuit to receive a bias current and generate an oscillating signal at an output node. A current differencing circuit subtracts a current at the output node from a reference current to generate a first current. In addition, a current mirroring circuit mirrors the first current to generate the bias current. An inverter stage is coupled to the output node, and includes an input branch configured to receive the oscillating signal and generate first and second control signals based upon the oscillating signal. At least one amplifying branch receives the first and second control signals and amplifies the first and second control signals. An output branch receives the amplified first and second control signals and generates an amplified version of the oscillating signal based upon the amplified first and second control signals.
Abstract translation: 电路包括用于接收偏置电流并在输出节点产生振荡信号的振荡器电路。 电流差分电路从参考电流中减去输出节点处的电流以产生第一电流。 此外，电流镜像电路反射第一电流以产生偏置电流。 逆变器级耦合到输出节点，并且包括被配置为接收振荡信号并基于振荡信号产生第一和第二控制信号的输入分支。 至少一个放大支路接收第一和第二控制信号并放大第一和第二控制信号。 输出分支接收放大的第一和第二控制信号，并且基于放大的第一和第二控制信号产生振荡信号的放大版本。
-
公开(公告)号：US09459447B2
公开(公告)日：2016-10-04
申请号：US14174367
申请日：2014-02-06
Applicant: STMicroelectronics International N.V.
Inventor： Moshe Medina , Pinchas Chaviv , Yaron Fein
CPC classification number: G02B26/08 , B81C1/00603 , G02B26/0841 , H02N1/008
Abstract: An apparatus is formed from a double active layer silicon on insulator (DSOI) substrate that includes first and second active layers separated by an insulating layer. An electrostatic comb drive is formed from the substrate to include a first comb formed from the first active layer and a second comb formed from the second active layer. The comb drive may be used to impart a tilting motion to a micro-mirror. The method of manufacturing provides comb teeth exhibiting an aspect ratio greater than 1:20, with an offset distance between comb teeth of the first and second combs that is less than about 6 μm.
Abstract translation: 一种由绝缘层双层有源层绝缘体（DSOI）衬底形成的装置包括由绝缘层隔开的第一和第二有源层。 从基板形成静电梳驱动器，以包括由第一有源层形成的第一梳和由第二有源层形成的第二梳。 梳状驱动器可用于向微镜提供倾斜运动。 制造方法提供梳齿显示大于1:20的纵横比，第一和第二梳的梳齿之间的偏移距离小于约6μm。
-
公开(公告)号：US09444440B2
公开(公告)日：2016-09-13
申请号：US13174574
申请日：2011-06-30
Applicant: Abhishek Jain , Kallol Chatterjee , Chittoor Parthasarathy , Saurabhkumar Singh
Inventor： Abhishek Jain , Kallol Chatterjee , Chittoor Parthasarathy , Saurabhkumar Singh
IPC: H04L7/02 , H03K5/1534 , H03K19/003
CPC classification number: H03K5/1534 , H03K19/00346
Abstract: An embodiment of a detector includes first and second generators. The first generator is operable to receive a transition of a first signal and to generate in response to the transition a first pulse having a length that is approximately equal to a length of a detection window. And the second generator is operable to receive a second signal and to generate a second pulse having a relationship to the first pulse in response to a transition of the second signal occurring approximately during the detection window.
Abstract translation: 检测器的实施例包括第一和第二发生器。 第一发生器可操作以接收第一信号的转换并且响应于转换而产生具有近似等于检测窗口的长度的长度的第一脉冲。 并且第二发生器可操作以响应于在检测窗口期间大致发生的第二信号的转变而接收第二信号并产生与第一脉冲具有关系的第二脉冲。
-
公开(公告)号：US09436432B2
公开(公告)日：2016-09-06
申请号：US11648113
申请日：2006-12-29
Applicant: Kapil Batra
Inventor： Kapil Batra
CPC classification number: G06F5/065 , G06F5/16 , G11C7/1075
Abstract: A memory may require a buffering mechanism in which data can be written and read at the same time. This requires a multi-port FIFO memory, which has multiple ports, thus providing simultaneous read & write operations. Multi-port memories have a large penalty on area. Hence, a technique is proposed for avoiding use of multi-port memories for designs which requires sequential read and write operations. In this technique multiple single-port memories are used to form a multi-port memory. This memory requires additional control logic but consumes significantly lower silicon area.
Abstract translation: 存储器可能需要缓冲机制，其中可以同时写入和读取数据。 这需要具有多个端口的多端口FIFO存储器，从而提供同时的读写操作。 多端口存储器面积受到很大的惩罚。 因此，提出了一种避免使用多端口存储器进行连续读取和写入操作的设计的技术。 在这种技术中，使用多个单端口存储器来形成多端口存储器。 该存储器需要额外的控制逻辑，但消耗明显较低的硅面积。
-
-
-
-
-
-
-
-
-
Search Results
1892
records
(took 0.215 seconds)
