公开(公告)号：US09813024B2

公开(公告)日：2017-11-07

申请号：US14985759

申请日：2015-12-31

Applicant: STMicroelectronics International N.V.

Inventor： Vinod Kumar

IPC: H03F1/02 ,  H01L29/78 ,  H01L29/94 ,  H01L29/66 ,  H01L21/84 ,  G05F3/16 ,  H03K17/687 ,  H03L7/093 ,  H03F3/193 ,  H01L29/786

CPC classification number: H03F1/0205 ,  G05F3/16 ,  H01L21/84 ,  H01L29/66181 ,  H01L29/7831 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/94 ,  H03F3/193 ,  H03F2200/451 ,  H03K17/687 ,  H03L7/093

Abstract: Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

公开(公告)号：US09800204B2

公开(公告)日：2017-10-24

申请号：US14219786

申请日：2014-03-19

Applicant: STMicroelectronics International N.V.

Inventor： Vinod Kumar

IPC: H03F1/02 ,  H01L29/78 ,  H01L29/94 ,  H01L29/66 ,  H01L21/84 ,  G05F3/16 ,  H03K17/687 ,  H03L7/093 ,  H03F3/193 ,  H01L29/786

CPC classification number: H03F1/0205 ,  G05F3/16 ,  H01L21/84 ,  H01L29/66181 ,  H01L29/7831 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/94 ,  H03F3/193 ,  H03F2200/451 ,  H03K17/687 ,  H03L7/093

Abstract: Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

公开(公告)号：US20160118986A1

公开(公告)日：2016-04-28

申请号：US14989052

申请日：2016-01-06

Applicant: STMicroelectronics International N.V

Inventor： Vinod Kumar ,  Saiyid Mohammad Irshad Rizvi

IPC: H03K19/0175 ,  H03K19/00

CPC classification number: H03K19/017545 ,  G06F1/329 ,  H03K19/0008 ,  Y02D10/24 ,  Y10T307/406

Abstract: An apparatus includes a first input/output (I/O) interface circuit having a maximum voltage rating. The first I/O interface circuit includes a level shifter and an output stage. A reference voltage bias generator is coupled to the first I/O interface circuit, to a first supply voltage, and to a first ground potential. The reference voltage bias generator is configured to generate a plurality of reference bias signals, including a first reference voltage and a second reference voltage. When the first supply voltage is not greater than the maximum voltage rating, the first reference voltage is equal to the first supply voltage and the second reference voltage is equal to the first ground potential. When the first supply voltage is greater than the maximum voltage rating, the first reference voltage is equal to the first supply voltage times a first fraction, and the second reference voltage is equal to the first supply voltage times a second fraction.

Abstract translation: 一种装置包括具有最大额定电压的第一输入/输出（I / O）接口电路。 第一I / O接口电路包括电平转换器和输出级。 参考电压偏置发生器耦合到第一I / O接口电路，耦合到第一电源电压和第一接地电位。 参考电压偏置发生器被配置为产生包括第一参考电压和第二参考电压的多个参考偏置信号。 当第一电源电压不大于最大额定电压时，第一参考电压等于第一电源电压，第二参考电压等于第一地电位。 当第一电源电压大于最大额定电压时，第一参考电压等于第一电源电压乘以第一分数，第二参考电压等于第一电源电压乘以第二分数。

公开(公告)号：US08981817B2

公开(公告)日：2015-03-17

申请号：US13926748

申请日：2013-06-25

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Vinod Kumar ,  Pradeep Kumar Badrathwal ,  Saiyid Mohammad Irshad Rizvi ,  Paras Garg ,  Kallol Chatterjee ,  Pierre Dautriche

IPC: H03K3/00

CPC classification number: H03K19/00384

Abstract: A circuit having a centralized PT compensation circuit to provide compensation signals to localized I/O blocks on the chip. Process variations and temperature variations tend to be approximately uniform across an integrated circuit chip. Thus, a single, centralized PT compensation circuit may be used instead of one PT compensation circuit per I/O section as with solutions of the past. Further, the PT compensation circuit may generate a digital code indicative of the effects of process and temperature. Further yet, each section of I/O block may have a local voltage compensation circuit to compensate the voltage variation of the I/O block. The voltage compensation circuit utilizes an independent reference voltage. The reference voltage is generated by the PT compensation circuit, which is placed centrally in the IC chip and hence any need to repeat the reference generation for each I/O block is eliminated.

Abstract translation: 具有集中PT补偿电路以向芯片上的局部I / O块提供补偿信号的电路。 整个集成电路芯片的工艺变化和温度变化趋向于大致均匀。 因此，与过去的解决方案一样，可以使用单个集中式PT补偿电路来代替每个I / O部分的一个PT补偿电路。 此外，PT补偿电路可以产生指示过程和温度的影响的数字代码。 此外，I / O块的每个部分可以具有用于补偿I / O块的电压变化的局部电压补偿电路。 电压补偿电路采用独立的参考电压。 参考电压由放置在IC芯片中央的PT补偿电路产生，因此不需要重复每个I / O块的参考生成。

公开(公告)号：US09467125B2

公开(公告)日：2016-10-11

申请号：US14573129

申请日：2014-12-17

Applicant: STMicroelectronics International N.V.

Inventor： Vinod Kumar ,  Saiyid Mohammad Irshad Rizvi

IPC: H03K3/3565

CPC classification number: H03K3/3565

Abstract: The Schmitt trigger circuit includes a signal input, a first inverter coupled to the signal input and configured to operate at a first voltage, and a second inverter coupled downstream of the first inverter and configured to operate at a second voltage lower than the first voltage. A protection device is coupled between the first inverter and the second inverter, and configured to limit a voltage input to the second inverter at the second voltage. A feedback circuit is coupled downstream of the protection device between the first inverter and the second inverter and configured to introduce hysteresis. An output circuit is coupled to the second inverter and configured to provide an output signal at the second voltage. The approach provides an architecture for 3.3V receivers designed by using 1.8V devices, without active power consumption from the I/O PAD during transition, and/or that supports CMOS standard levels for 1.8V and 3.3V receivers.

Abstract translation: 施密特触发电路包括信号输入端，耦合到信号输入并被配置为以第一电压工作的第一反相器，以及耦合在第一反相器下游的第二反相器，并被配置为在低于第一电压的第二电压下工作。 保护装置耦合在第一反相器和第二反相器之间，并且被配置为将第二反相器的电压输入限制在第二电压。 反馈电路被耦合在第一逆变器和第二逆变器之间的保护装置的下游，并被配置为引入滞后。 输出电路耦合到第二反相器并且被配置为提供处于第二电压的输出信号。 该方法为通过使用1.8V器件设计的3.3V接收器提供了架构，在转换期间没有来自I / O PAD的有功功耗，和/或支持1.8V和3.3V接收器的CMOS标准电平。

公开(公告)号：US20160112011A1

公开(公告)日：2016-04-21

申请号：US14985759

申请日：2015-12-31

Applicant: STMicroelectronics International N.V.

Inventor： Vinod Kumar

IPC: H03F1/02 ,  H03F3/193 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H03F1/0205 ,  G05F3/16 ,  H01L21/84 ,  H01L29/66181 ,  H01L29/7831 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/94 ,  H03F3/193 ,  H03F2200/451 ,  H03K17/687 ,  H03L7/093

Abstract: Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

公开(公告)号：US20150270393A1

公开(公告)日：2015-09-24

申请号：US14219786

申请日：2014-03-19

Applicant: STMicroelectronics International N.V.

Inventor： Vinod Kumar

IPC: H01L29/78 ,  H01L29/94 ,  H01L29/66 ,  H03K17/687 ,  H01L29/06 ,  H03L7/08 ,  G05F3/16 ,  H01L29/36 ,  H01L21/84

CPC classification number: H03F1/0205 ,  G05F3/16 ,  H01L21/84 ,  H01L29/66181 ,  H01L29/7831 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/94 ,  H03F3/193 ,  H03F2200/451 ,  H03K17/687 ,  H03L7/093

Abstract: Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

Abstract translation: 双栅极FD-SOI晶体管用作MOSFET电容器来替代模拟微电路中的无源阱电容器。 双栅极FD-SOI器件的使用有助于减少不稳定的振荡并提高电路性能。 在FD-SOI晶体管的衬底内的厚的掩埋氧化物层形成电容电介质，其能够维持高于晶体管阈值电压的1.2V-3.3V范围内的高工作电压。 FD-SOI晶体管中的次级栅极用于从背面产生通道，使得即使当第一栅极上的偏置电压较小时，有效电容仍然较高。 掩埋氧化物层的电容进一步用作电源和地之间的去耦电容器。 在一个示例中，双栅极PMOS-FD-SOI晶体管耦合到运算放大器和高电压输出驱动器以产生精密控制的电压基准发生器。 在另一示例中，两个双栅极PMOS和一个双栅极NMOS FD-SOI晶体管耦合到电荷泵，相位频率检测器和电流控制振荡器，以产生高性能锁相环电路，其中去耦电容器 与常规使用的无源阱电容相比，占地面积更小。

公开(公告)号：US09013212B2

公开(公告)日：2015-04-21

申请号：US13931343

申请日：2013-06-28

Applicant: STMicroelectronics International N.V.

Inventor： Vinod Kumar

IPC: H03B1/00 ,  G11C7/10 ,  H03K3/02

CPC classification number: H03K3/02 ,  G11C7/1057 ,  G11C7/1069

Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.

Abstract translation: 输出驱动器电路包括具有公共电流路径的第一，第二，第三和第四晶体管，其中第一晶体管的栅极接收第一开关信号，第二晶体管的栅极接收第一参考电压，第三晶体管的栅极 晶体管接收第二参考电压，并且第四晶体管的栅极接收第二开关信号，并且其中第一电容器耦合在第一晶体管的栅极和第三晶体管的栅极之间，第二电容器耦合在栅极之间 的第二晶体管和第四晶体管的栅极，并且在耦合第二和第三晶体管的节点处提供输出信号。

公开(公告)号：US10187011B2

公开(公告)日：2019-01-22

申请号：US15713145

申请日：2017-09-22

Applicant: STMicroelectronics International N.V.

Inventor： Vinod Kumar

IPC: H01L27/108 ,  H01L29/94 ,  H03F1/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84 ,  G05F3/16 ,  H03K17/687 ,  H03L7/093 ,  H03F3/193 ,  H01L29/786

Abstract: Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

公开(公告)号：US09762243B2

公开(公告)日：2017-09-12

申请号：US14989052

申请日：2016-01-06

Applicant: STMicroelectronics International N.V

Inventor： Vinod Kumar ,  Saiyid Mohammad Irshad Rizvi

IPC: H03K19/01 ,  H03K19/00 ,  H03K19/0175 ,  G06F1/32

CPC classification number: H03K19/017545 ,  G06F1/329 ,  H03K19/0008 ,  Y02D10/24 ,  Y10T307/406

Abstract: An apparatus includes a first input/output (I/O) interface circuit having a maximum voltage rating. The first I/O interface circuit includes a level shifter and an output stage. A reference voltage bias generator is coupled to the first I/O interface circuit, to a first supply voltage, and to a first ground potential. The reference voltage bias generator is configured to generate a plurality of reference bias signals, including a first reference voltage and a second reference voltage. When the first supply voltage is not greater than the maximum voltage rating, the first reference voltage is equal to the first supply voltage and the second reference voltage is equal to the first ground potential. When the first supply voltage is greater than the maximum voltage rating, the first reference voltage is equal to the first supply voltage times a first fraction, and the second reference voltage is equal to the first supply voltage times a second fraction.