公开(公告)号：US20220343980A1

公开(公告)日：2022-10-27

申请号：US17723204

申请日：2022-04-18

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Shohei Kamisaka ,  Vinod Purayath

IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: A process for fabricating a three-dimensional NOR memory string of storage transistors implements a channel-last fabrication process with channel replacement using silicon germanium (SiGe). In particular, the process uses silicon germanium as a sacrificial layer, to be replaced with the channel material after the charge-storage layer of the storage transistors is formed. In this manner, the channel region is prevented from experiencing excessive high-temperature processing steps, such as during the annealing of the charge-storage layer.

公开(公告)号：US20220328518A1

公开(公告)日：2022-10-13

申请号：US17809535

申请日：2022-06-28

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Scott Brad Herner ,  Wu-Yi Henry Chien ,  Jie Zhou ,  Eli Harari

IPC: H01L27/11582 ,  H01L29/66 ,  H01L21/308

Abstract: Various methods overcome the limitations and achieve superior scaling by (i) replacing a single highly challenging high aspect ratio etch step with two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips, (ii) using dielectric pillars for support and to maintain structural stability during a high aspect ratio etch step and subsequent processing steps, or (iii) using multiple masking steps to provide two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips.

公开(公告)号：US20220293623A1

公开(公告)日：2022-09-15

申请号：US17804986

申请日：2022-06-01

Applicant: SunRise Memory Corporation

Inventor： Tianhong Yan ,  Scott Brad Herner ,  Jie Zhou ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L27/11573 ,  H01L27/11565 ,  H01L29/45 ,  H01L23/528 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/225 ,  H01L29/786 ,  H01L29/66 ,  H01L27/11582

Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

公开(公告)号：US20220254390A1

公开(公告)日：2022-08-11

申请号：US17666255

申请日：2022-02-07

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Dean Gans ,  Aran Ziv

IPC: G11C7/10 ,  H03K19/20

Abstract: A memory module including a memory array of storage transistors and a control circuit where the control circuit includes a memory interface for providing high bandwidth access to the memory array on serial data lanes. In some embodiments, the control circuit of a memory module includes multiple transceivers for connecting to serial data lanes. In one embodiment, the memory interface of a memory module configures some transceivers for host connection or for upstream connection to an upstream memory module and configures other transceivers for downstream connection to a downstream memory module. In other embodiments, a multi-module memory device is formed using multiple memory modules connected in a cascade configuration or in a star configuration to provide high bandwidth memory access to all memory locations of the multiple memory modules using the given number of serial data lanes of the host connection.

公开(公告)号：US20220199532A1

公开(公告)日：2022-06-23

申请号：US17548034

申请日：2021-12-10

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Shohei Kamisaka ,  Yosuke Nosho

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: A conductor-filled via formed between an interconnection conductor layer and a buried contact above a planar surface of a semiconductor substrate, includes: (a) a first portion that extends from the interconnection conductor layer through a first isolation layer to a step in a staircase structure formed above the buried contacts, wherein (i) the step of the staircase structure is aligned to the buried contact along a first direction substantially normal to the planar surface of the semiconductor substrate, (ii) at the top of the step, the step comprises a bit line layer, a source line layer and a second isolation layer between the bit line layer and the source line layer, and (iii) the first portion electrically contacting the layer at the top of the step; and (b) a second portion extending from a portion of the step below the layer at the top of the step to the buried contact, wherein a spacer insulator lines sidewalls of the conductor-filled via.

公开(公告)号：US20220180943A1

公开(公告)日：2022-06-09

申请号：US17529083

申请日：2021-11-17

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Raul Adrian Cernea

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/08

Abstract: A semiconductor memory device is implemented as a string of storage transistors with sense amplifier connected drain terminals and floating source terminals. In some embodiments, a method in the semiconductor memory device applies a bit line control (BLC) voltage with a voltage step down to the bias device during the read operation to reduce the settling time on the bit line, thereby shortening the access time for data read out from the storage transistors. In other embodiments, a method in the semiconductor memory device including an array of strings of storage transistors uses a current from a biased but unselected bit line as the sense amplifier reference current for reading stored data from a selected bit line. In one embodiment, the sense amplifier reference current is provided to a referenced sense amplifier to generate a sense amplifier data latch signal.

公开(公告)号：US11315645B2

公开(公告)日：2022-04-26

申请号：US16820209

申请日：2020-03-16

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari

IPC: G11C16/34 ,  G11C11/56 ,  H01L29/10 ,  G11C16/04 ,  H01L29/08 ,  H01L29/786 ,  H01L29/92 ,  H01L27/11582 ,  G11C16/10 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11565

Abstract: Multi-gate NOR flash thin-film transistor (TFT) string arrays are organized as 3-dimensional stacks of active strips. Each active strip includes a shared source sublayer and a shared drain sublayer that is connected to substrate circuits. Data storage in the active strip is provided by charge-storage elements between the active strip and a multiplicity of control gates provided by adjacent local word-lines. The parasitic capacitance of each active strip is used to eliminate hard-wire ground connection to the shared source making it a semi-floating, or virtual source. Pre-charge voltages temporarily supplied from the substrate through a single port per active strip provide the appropriate voltages on the source and drain required during read, program, program-inhibit and erase operations. TFTs on multiple active strips can be pre-charged separately and then read, programmed or erased together in a massively parallel operation.

公开(公告)号：US20220077189A1

公开(公告)日：2022-03-10

申请号：US17530792

申请日：2021-11-19

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Scott Brad Herner ,  Eli Harari

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: A process for forming an antimony-doped silicon-containing layer includes: (a) depositing by chemical vapor deposition the antimony-doped silicon-containing layer above a semiconductor structure, using an antimony source gas and a silicon source gas or a combination of the silicon source gas and a germanium source gas; and (b) annealing the antimony-doped silicon-containing layer at a temperature of no greater than 800° C. The antimony source gas may include one or more of: trimethylantimony (TMSb) and triethylantimony (TESb). The silicon source gas comprises one or more of: silane, disilane, trichlorosilane, (TCS), dichlorosilane (DCS), monochlorosilane (MCS), methylsilane, and silicon tetrachloride. The germanium source gas comprises germane.

公开(公告)号：US20220028886A1

公开(公告)日：2022-01-27

申请号：US17382126

申请日：2021-07-21

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Vinod Purayath ,  Yosuke Nosho ,  Shohei Kamisaka ,  Michiru Nakane ,  Eli Harari

IPC: H01L27/11582 ,  H01L29/51 ,  H01L21/28

Abstract: A process for building a 3-Dimensional NOR memory array avoids the challenge of etching a conductor material that is aimed at providing local word lines at a fine pitch. The process defines the local word lines between isolation shafts that may be carried out at a lower aspect ratio than would be required for etching the conductor material.

公开(公告)号：US20210407983A1

公开(公告)日：2021-12-30

申请号：US17470861

申请日：2021-09-09

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Scott Brad Herner ,  Eli Harari

IPC: H01L25/18 ,  H01L25/065

Abstract: A memory array and single-crystal circuitry are provided by wafer bonding (e.g., adhesive wafer bonding or anodic wafer bonding) in the same integrated circuit and interconnected by conductors of a interconnect layer. Additional circuitry or memory arrays may be provided by additional wafer bonds and electrically connected by interconnect layers at the wafer bonding interface. The memory array may include storage or memory transistors having single-crystal epitaxial silicon channel material.