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公开(公告)号：US12138338B2
公开(公告)日：2024-11-12
申请号：US16466738
申请日：2017-12-20
Applicant: L'OREAL
Inventor： Gwenaëlle Jegou
Abstract: The invention relates to a cosmetic process for treating keratin fibres, comprising: (i) a step of applying to the keratin fibres a cosmetic composition containing a polyvinyl alcohol polymer comprising:—an alcohol unit—optionally an acetate unit—a photocrosslinkable unit—a hydrophobic unit; (ii) a step of irradiating the composition on the keratin fibres to crosslink said polymer. The invention also relates to the novel polyvinyl alcohol polymer used in said process. The treated keratin fibres have good cosmetic properties in terms of a soft feel and disentangling, which properties are persistent after one or more shampoo washes.
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22.发明授权公开(公告)号：US12136457B2
公开(公告)日：2024-11-05
申请号：US18354565
申请日：2023-07-18
Inventor： Katherine H. Chiang , Chung-Te Lin
IPC: G11C11/24 , G11C11/4091 , G11C11/4096 , G11C11/56 , H01L27/12 , H01L29/66 , H01L29/786 , H01L49/02 , H10B99/00
Abstract: A memory device may include at least one multinary memory cell. Each multinary memory cell includes a parallel connection of N sub-bit units. N is an integer greater than 1. Each of the N sub-bit units includes a series connection of a respective transistor and a respective capacitor. A first sub-bit unit includes a first capacitor having a capacitance of C, and each i-th sub-unit includes an i-th capacitor having a capacitance of about 2i-1×C. A multinary bit having 2N values may be stored. A device network including multiple multinary logic units is also provided. Each of multiple multinary logic unit includes a parallel connection of N sub-bit units. Each sub-bit unit includes a series connection of a respective transistor and a respective capacitor having capacitance ratios of powers of 2.
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公开(公告)号：US12131915B2
公开(公告)日：2024-10-29
申请号：US18325905
申请日：2023-05-30
Inventor： Jheng-Hong Jiang , Chia-Wei Liu , Shing-Huang Wu
IPC: H01L21/321 , C22C21/12 , H01L21/768 , H01L23/522 , H01L23/532
CPC classification number: H01L21/3212 , C22C21/12 , H01L21/76802 , H01L21/7684 , H01L21/76843 , H01L21/76877 , H01L23/5226 , H01L23/53219 , H01L23/53223
Abstract: A cavity may be formed in a dielectric material layer overlying a substrate. A layer stack including a metallic barrier liner, a metallic fill material layer, and a metallic capping material may be deposited in the cavity and over the dielectric material layer. Portions of the layer stack located above a horizontal plane including a top surface of the dielectric material layer may be removed. A contiguous set of remaining material portions of the layer stack includes a metal interconnect structure that is free of a pitted surface.
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24.发明授权公开(公告)号：US12124270B2
公开(公告)日：2024-10-22
申请号：US17265455
申请日：2018-09-15
Applicant: QUALCOMM Incorporated
Inventor： Jun Liu , Zixiang Wang , Weizhang Luo , Mei Wu Fang , Tiequan Luo
CPC classification number: G05D1/0253 , G06T7/20 , G06T7/70
Abstract: Various embodiments include methods for improving navigation by a processor of a robotic device equipped with an image sensor and an optical flow sensor. The robotic device may be configured to capture or receive two image frames from the image sensor, generate a homograph computation based on the image frames, receive optical flow sensor data from an optical flow sensor, and determine a scale estimation value based on the homograph computation and the optical flow sensor data. The robotic device may determine the robotic device pose (or the pose of the image sensor) based on the scale estimation value.
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公开(公告)号：US12121615B2
公开(公告)日：2024-10-22
申请号：US17267541
申请日：2020-01-08
Applicant: ATLANGRAM
Inventor： Olivier Meyer , Amokrane Reghal
CPC classification number: A61K9/5123 , A61K9/5153 , A61K9/5161 , A61K38/12 , A61P19/00 , A61P31/04
Abstract: The present invention relates to a pharmaceutical composition stabilized in a gelled state at at least a temperature varying from 15° C. to 40° C., comprising at least one aqueous phase gelled with at least one hydrophilic polymeric gelling agent, lipid nanocapsules comprising a liquid or semi-liquid lipid core at room temperature enveloped in a lipid envelope which is solid at room temperature, said gelled aqueous phase and nanocapsules containing at least one antibiotic, identical or different, the antibiotic in said aqueous phase being present there in the form of a solute.
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Patent Agency Ranking
公开(公告)号：US12119482B2
公开(公告)日：2024-10-15
申请号：US17322181
申请日：2021-05-17
Applicant: NANOGRAF CORPORATION
Inventor： Cary Michael Hayner , Aaron Yost , Kathryn Hicks , Seonbaek Ha , Pitawat Mahawattanangul , Joshua J. Lau
IPC: H01M4/133 , H01M4/134 , H01M4/136 , H01M4/36 , H01M4/38 , H01M4/48 , H01M4/58 , H01M4/583 , H01M4/587 , H01M4/62 , H01M10/0525 , H01M4/02
CPC classification number: H01M4/366 , H01M4/133 , H01M4/134 , H01M4/136 , H01M4/382 , H01M4/386 , H01M4/483 , H01M4/5825 , H01M4/587 , H01M4/622 , H01M10/0525 , H01M2004/027
Abstract: Active material composite particles, an electrode including the composite particles, a lithium ion secondary battery including the electrode, and method of forming the same, in which the composite particles each include a core particle including an alkali metal or an alkali earth metal silicate, and a coating disposed on the surface of the core particle. The coating includes turbostratic carbon having a Raman spectrum having: a D band having a peak intensity (ID) at wave number between 1330 cm−1 and 1360 cm−1; a G band having a peak intensity (IG) at wave number between 1580 cm−1 and 1600 cm−1; and a 2D band having a peak intensity (I2D) at wave number between 2650 cm−1 and 2750 cm−1, wherein a ratio of ID/IG ranges from greater than zero to about 1.1, and a ratio of I2D/IG ranges from about 0.4 to about 2.
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公开(公告)号：US12113099B2
公开(公告)日：2024-10-08
申请号：US18359023
申请日：2023-07-26
Inventor： Fu-Chiang Kuo
IPC: H01G4/35 , H01L23/532 , H01L49/02 , H01L21/285 , H01L29/94
CPC classification number: H01L28/60 , H01G4/35 , H01L21/2855 , H01L23/5329 , H01L28/91 , H01L29/945
Abstract: A deep trench is formed in a substrate. A layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers is formed over the substrate. The layer stack continuously extends into the deep trench, and a cavity is present in an unfilled volume of the deep trench. A dielectric fill material layer including a dielectric fill material is formed in the cavity and over the substrate. The dielectric fill material layer encapsulates a void that is free of any solid phase and is formed within a volume of the cavity. The void may expand or shrink under stress during subsequently handling of a deep trench capacitor including the layer stack to absorb mechanical stress and to increase mechanical stability of the deep trench capacitor.
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公开(公告)号：US12112321B2
公开(公告)日：2024-10-08
申请号：US16699071
申请日：2019-11-28
Applicant: QUALCOMM Incorporated
Inventor： Prakash Tiwari , Shvetank Kumar Singh , Rajesh Yadav , Naga Chandan Babu Gudivada , Vidyasagar Gopireddy , Manish Sharma , Utkarsh Mehta
IPC: G06Q20/32 , G06F9/451 , G06F16/23 , G06F21/53 , G06F21/57 , G06Q20/10 , G06Q20/36 , G06Q20/38 , G06Q20/40 , G06Q40/06 , H04L29/06 , H04W12/06 , H04W12/08 , G06F21/31 , G06F21/32 , G06F21/45 , G06Q20/34 , G06Q40/02 , H04W4/14 , H04W12/062 , H04W12/72 , H04W60/00
CPC classification number: G06Q20/3823 , G06F9/451 , G06F21/53 , G06F21/57
Abstract: Various embodiments include methods and devices for implementing a secure user interface. The method may include generating a secure user interface display in a secure execution environment, generating a non-secure display in a normal execution environment, combining the secure user interface and the non-secure display into a combined display, and presenting the combined display via a display device.
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公开(公告)号：US12101936B2
公开(公告)日：2024-09-24
申请号：US17523487
申请日：2021-11-10
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Tatsuya Hinoue , Yusuke Mukae , Ryousuke Itou , Masanori Tsutsumi , Akio Nishida , Ramy Nashed Bassely Said
IPC: H01L27/11582 , H10B41/27 , H10B43/27
Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.
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30.发明授权公开(公告)号：US12100730B2
公开(公告)日：2024-09-24
申请号：US18501396
申请日：2023-11-03
Inventor： Po-Chia Lai , Stefan Rusu , Chun-Yen Lee
IPC: H01L23/522 , H01L21/768 , H01L27/08 , H01L49/02
CPC classification number: H01L28/60 , H01L21/76838 , H01L23/5223 , H01L23/5226 , H01L27/0805
Abstract: Integrated circuit (IC) devices include a metal-insulator-metal (MIM) capacitor having a top electrode plate, a bottom electrode plate, and a plurality of intermediate electrode plates between the top electrode plate and the bottom electrode plate. A plurality of dielectric layers may separate each of the electrode plates of the MIM capacitor from adjacent plates of the MIM capacitor. Each of the intermediate electrode plates may have a thickness that is greater than a thickness of the top electrode plate and the bottom electrode plate. By providing multiple intermediate electrode plates between the top and bottom electrode plates of the MIM capacitor, and allocating the greatest plate thicknesses to the intermediate plates, the capacitance density may be increased in a given area of the IC device, which may provide increased performance for the IC device.
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