公开(公告)号：US07737725B1

公开(公告)日：2010-06-15

申请号：US12098400

申请日：2008-04-04

Applicant: Ahmad R. Ansari ,  Kam-Wing Li

Inventor： Ahmad R. Ansari ,  Kam-Wing Li

IPC: G06F7/38 ,  H03K19/173

CPC classification number: G06F15/7867

Abstract: A device control register controller for a processor block Application Specific Integrated Circuit (“ASIC”) core is described. Device control register slave blocks are coupled to the device control register controller and have access to device registers for a plurality of interfaces of the processor block ASIC core. A master device interface is for coupling at least one slave device external to the processor block ASIC core to the device control register controller. A slave device interface is for coupling a master device external to the processor block ASIC core to the device control register controller.

Abstract translation: 描述了用于处理器块的设备控制寄存器控制器专用集成电路（“ASIC”）核心。 器件控制寄存器从器件块耦合到器件控制寄存器控制器，并且可以访问处理器块ASIC核心的多个接口的器件寄存器。 主设备接口用于将处理器块ASIC核心外部的至少一个从设备耦合到设备控制寄存器控制器。 从设备接口用于将处理器块ASIC核心外部的主设备耦合到设备控制寄存器控制器。

公开(公告)号：US07673087B1

公开(公告)日：2010-03-02

申请号：US12057322

申请日：2008-03-27

Applicant: Ahmad R. Ansari ,  Jeffery H. Applebaum ,  Kunal R. Shenoy

Inventor： Ahmad R. Ansari ,  Jeffery H. Applebaum ,  Kunal R. Shenoy

IPC: G06F13/14

CPC classification number: G06F13/366 ,  Y10S370/911

Abstract: Arbitration for a processor block core is described. Master devices are associated with a processor block core embedded in a host integrated circuit (“IC”). The master devices are coupled to core logic of the host IC via a crossbar switch and a bridge, which are part of the processor block core. The crossbar switch includes an arbiter. An arbitration protocol is selected from among a plurality of arbitration protocols for use by the arbiter. Pending transactions having are polled for access to the bridge for arbitration using the arbitration protocol selected.

Abstract translation: 描述了处理器块核心的仲裁。 主设备与嵌入在主机集成电路（“IC”）中的处理器块核心相关联。 主设备通过作为处理器块核心的一部分的交叉开关和桥接器耦合到主机IC的核心逻辑。 交叉开关包括仲裁器。 仲裁协议是从仲裁器中使用的仲裁协议中选出的。 被审查的待处理事务被轮询以使用所选择的仲裁协议访问该桥以进行仲裁。

公开(公告)号：US07200723B1

公开(公告)日：2007-04-03

申请号：US10913282

申请日：2004-08-06

Applicant: Ahmad R. Ansari ,  Kathryn Story Purcell

Inventor： Ahmad R. Ansari ,  Kathryn Story Purcell

IPC: G06F12/00

CPC classification number: G06F12/063 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/355 ,  G06F9/3822 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3877 ,  G06F9/3897

Abstract: An interface for accessing a bank of registers is described. A controller is coupled to receive address information, read information and write information. The device control register interface includes: a data bus for receiving data, pointer information and operation delineation information; a decoder coupled to receive the read information, the write information, the pointer information and the operation delineation information, where the decoder is configured to provide activation signaling responsive to information received; and the bank of registers coupled to the decoder to receive the activation signaling and coupled to the data bus for receiving the data, where the address information is for the bank or registers and where a single address is used for accessing all registers in the bank of registers.

Abstract translation: 描述用于访问一组寄存器的接口。 控制器被耦合以接收地址信息，读取信息和写入信息。 设备控制寄存器接口包括：用于接收数据的数据总线，指针信息和操作描画信息; 耦合以接收读取信息，写入信息，指针信息和操作描绘信息的解码器，其中解码器被配置为响应于所接收的信息提供激活信令; 以及耦合到解码器的寄存器组，以接收激活信令并耦合到数据总线以接收数据，其中地址信息用于存储体或寄存器，并且其中单个地址用于访问存储体中的所有寄存器 注册

公开(公告)号：US06886092B1

公开(公告)日：2005-04-26

申请号：US10001871

申请日：2001-11-19

Applicant: Stephen M. Douglass ,  Ahmad R. Ansari

Inventor： Stephen M. Douglass ,  Ahmad R. Ansari

IPC: G06F9/38 ,  G06F9/44 ,  G06F15/00 ,  G06F15/78

CPC classification number: G06F15/7867 ,  G06F9/3877 ,  G06F9/3897

Abstract: A method and apparatus for processing data within a programmable gate array begins when a fixed logic processor that is embedded within the programmable gate array detects a custom operation code. The processing continues when the fixed logic processor provides an indication of the custom operational code to the programmable gate array. The processing continues by having at least a portion of the programmable gate array, which is configured as a dedicated processor, performing a fixed logic routine upon receiving the indication from the fixed logic processor.

Abstract translation: 当可编程门阵列中嵌入的固定逻辑处理器检测到定制操作代码时，开始用于处理可编程门阵列内的数据的方法和装置。 当固定逻辑处理器向可编程门阵列提供自定义操作码的指示时，该处理继续。 该处理通过将可配置为专用处理器的可编程门阵列的至少一部分在从固定逻辑处理器接收到指示时执行固定逻辑例程而继续进行。

公开(公告)号：US08019950B1

公开(公告)日：2011-09-13

申请号：US12056954

申请日：2008-03-27

Applicant: Alex S. Warshofsky ,  Ahmad R. Ansari

Inventor： Alex S. Warshofsky ,  Ahmad R. Ansari

IPC: G06F13/00

CPC classification number: G06F13/1642 ,  G06F13/1678 ,  G06F2213/0038

Abstract: A method for address acknowledgement is described. A memory controller interface is embedded as part of an embedded core in a host integrated circuit. Access to the memory controller interface is arbitrated with an arbiter. An accept signal is sent from the memory controller interface to the arbiter to indicate whether the memory controller interface is ready to receive a transaction. Access to the memory controller interface is requested by a master device for passing the transaction to a memory controller via the arbiter. The arbiter is a proxy for the memory controller interface responsive to the accept signal being asserted. An acknowledgement signal is sent from the arbiter as a proxy for the memory controller interface responsive to receipt of the transaction and the accept signal being asserted.

Abstract translation: 描述地址确认的方法。 存储器控制器接口作为嵌入式核心的一部分嵌入在主机集成电路中。 存储器控制器接口的访问由仲裁器仲裁。 接收信号从存储器控制器接口发送到仲裁器，以指示存储器控制器接口是否准备好接收事务。 由主设备请求对存储器控制器接口的访问，以通过仲裁器将事务传递到存储器控制器。 仲裁器是响应于接受信号被断言的存储器控​​制器接口的代理。 响应于接收到交易并且接受信号被断言，确认信号作为代理存储器控制器接口从仲裁器发送。

公开(公告)号：US07970977B1

公开(公告)日：2011-06-28

申请号：US12363610

申请日：2009-01-30

Applicant: Kam-Wing Li ,  Ahmad R. Ansari ,  Sanford L. Helton ,  Tomai Knopp ,  Khang Kim Dao ,  Jeffrey H. Seltzer

Inventor： Kam-Wing Li ,  Ahmad R. Ansari ,  Sanford L. Helton ,  Tomai Knopp ,  Khang Kim Dao ,  Jeffrey H. Seltzer

IPC: G06F13/36 ,  G06F3/00 ,  G06F5/00 ,  G06F9/26

CPC classification number: G06F13/4036

Abstract: A method of bridging a plurality of buses within a bus bridge can include determining whether a queue of the bus bridge includes a transaction request directed to a restricted address range and, for each received transaction request, determining whether an address to which the transaction request is directed is within the restricted address range. Each transaction request received by the bus bridge can be selectively rejected according to whether the address to which the transaction request is directed is within the restricted address range and whether the queue includes a transaction request directed to the restricted address range.

Abstract translation: 桥接总线桥内的多个总线的方法可以包括确定总线桥的队列是否包括指向受限地址范围的事务请求，并且对于每个接收的事务请求，确定事务请求的地址是否为 指示在受限地址范围内。 可以根据交易请求所针对的地址是否在受限地址范围内以及该队列是否包括指向受限地址范围的交易请求，来选择性地拒绝总线桥接器接收的每个交易请求。

公开(公告)号：US07269805B1

公开(公告)日：2007-09-11

申请号：US10836995

申请日：2004-04-30

Applicant: Ahmad R. Ansari ,  Mehul R. Vashi ,  Nigel G. Herron ,  Stephen M. Douglass

Inventor： Ahmad R. Ansari ,  Mehul R. Vashi ,  Nigel G. Herron ,  Stephen M. Douglass

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F11/27

Abstract: Method and apparatus for generating a test program for an integrated circuit having an embedded processor. One embodiment has a system which includes an embedded microprocessor; a plurality of assembly language instructions stored in a memory, where the assembly language instructions substantially exercise a critical path or a path closest to the critical path in the embedded microprocessor; and programmable test circuitry having a programmable clock circuit for providing a multiplied clock signal to the embedded microprocessor in order to execute the assembly language instructions.

Abstract translation: 用于生成具有嵌入式处理器的集成电路的测试程序的方法和装置。 一个实施例具有包括嵌入式微处理器的系统; 存储在存储器中的多个汇编语言指令，其中所述汇编语言指令基本上行使关键路径或最接近所述嵌入式微处理器中的关键路径的路径; 以及具有可编程时钟电路的可编程测试电路，用于向嵌入式微处理器提供倍增时钟信号，以执行汇编语言指令。

公开(公告)号：US07194600B2

公开(公告)日：2007-03-20

申请号：US11059748

申请日：2005-02-17

Applicant: Stephen M. Douglass ,  Ahmad R. Ansari

Inventor： Stephen M. Douglass ,  Ahmad R. Ansari

IPC: G06F9/44

CPC classification number: G06F15/7867 ,  G06F9/3877 ,  G06F9/3897

Abstract: A method and apparatus for processing data within a programmable gate array comprise a first fixed logic processor and a second fixed logic processor that are embedded within the programmable gate array and detect a custom operation code. The processing continues when a fixed logic processor provides an indication of the custom operational code to the programmable gate array. The processing continues by having at least a portion of the programmable gate array, which is configured as a dedicated processor, performing a fixed logic routine upon receiving the indication from the fixed logic processor.

Abstract translation: 用于在可编程门阵列内处理数据的方法和装置包括嵌入可编程门阵列内并检测定制操作码的第一固定逻辑处理器和第二固定逻辑处理器。 当固定逻辑处理器向可编程门阵列提供自定义操作码的指示时，处理继续。 该处理通过将可配置为专用处理器的可编程门阵列的至少一部分在从固定逻辑处理器接收到指示时执行固定逻辑例程而继续进行。

公开(公告)号：US06973405B1

公开(公告)日：2005-12-06

申请号：US10153980

申请日：2002-05-22

Applicant: Ahmad R. Ansari

Inventor： Ahmad R. Ansari

IPC: G06F11/263 ,  G06F11/277

CPC classification number: G06F11/263

Abstract: A verification agent can be used to verify hard and/or soft modules under test in an integrated circuit. The integrated circuit contains a processor and memory for storing code executable by the processor. The module under test performs predetermined operations. The verification agent interacts with the module under test, including sending signals to the module under test and generating results based on the interaction. The code causes the processor to receive the results and compare the results with expected values. The module under test may be deemed to operate properly if the actual results match the expected values.

Abstract translation: 验证代理可用于在集成电路中验证被测试的硬和/或软模块。 集成电路包含处理器和用于存储可由处理器执行的代码的存储器。 被测模块执行预定的操作。 验证代理与被测模块进行交互，包括将信号发送给被测模块，并根据交互产生结果。 该代码使处理器接收结果并将结果与​​预期值进行比较。 如果实际结果符合预期值，则被测模块可能会被视为正常运行。

公开(公告)号：US06693452B1

公开(公告)日：2004-02-17

申请号：US10082883

申请日：2002-02-25

Applicant: Ahmad R. Ansari ,  Stephen M. Douglass

Inventor： Ahmad R. Ansari ,  Stephen M. Douglass

IPC: H03K19177

CPC classification number: H03K19/1776 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

Abstract: Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interconnecting logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and the interconnects of the programmable logic fabric. The interconnecting logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric. The invention is directed towards the various needs and requirements of the layout and floor planning of a device having both fixed logic circuitry and programmable logic circuitry. The various designs are geared towards many goals including allowing fail-safe operation, facilitating the ease of interface between fixed logic circuitry and programmable logic fabric, among other issues.

Abstract translation: 互连逻辑提供嵌入式固定逻辑电路或电路与可编程门阵列的可编程逻辑结构的连接，使得固定逻辑电路用作可编程逻辑结构的扩展。 互连逻辑包括互连瓦片，并且还可以包括互连逻辑。 互连瓦片提供固定逻辑电路的输入和/或输出与可编程逻辑结构的互连之间的选择性连接。 当互连逻辑包含时，提供了逻辑电路，用于调节固定逻辑电路和可编程逻辑结构之间的数据传输。 本发明针对具有固定逻辑电路和可编程逻辑电路的设备的布局和楼层规划的各种需求和要求。 各种设计旨在实现许多目标，包括允许故障安全操作，便于固定逻辑电路和可编程逻辑架构之间的接口以及其他问题。