公开(公告)号：US07081413B2

公开(公告)日：2006-07-25

申请号：US10763688

申请日：2004-01-23

Applicant: Bor-Wen Chan ,  Baw-Ching Perng ,  Ying-Tsung Chen

Inventor： Bor-Wen Chan ,  Baw-Ching Perng ,  Ying-Tsung Chen

IPC: H01L21/461 ,  H01L21/302

CPC classification number: H01L29/66545 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/6656

Abstract: A method for forming an ultra narrow semiconductive gate structure utilizes a tapered hardmask covered by an oxide liner. The tapered hardmask is formed over the semiconductive gate material by tapered etching. After the tapered hardmask structure is formed over the semiconductive material, an oxide layer is formed over the tapered hardmask. A sequence of highly selective etch operations are carried out to etch uncovered portions of the semiconductive gate material while the portions of the gate material covered by the tapered hardmask and oxide film remain unetched to form ultra narrow gate structures.

Abstract translation: 用于形成超窄半导体栅极结构的方法利用由氧化物衬垫覆盖的锥形硬掩模。 通过锥形蚀刻在半导体栅极材料上形成锥形硬掩模。 在半导体材料上形成锥形硬掩模结构之后，在锥形硬掩模上形成氧化物层。 执行高选择性蚀刻操作的序列以蚀刻半导体栅极材料的未覆盖部分，同时由锥形硬掩模和氧化物膜覆盖的栅极材料的部分保持未蚀刻以形成超窄栅极结构。

公开(公告)号：US20050253204A1

公开(公告)日：2005-11-17

申请号：US10846278

申请日：2004-05-13

Applicant: Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

Inventor： Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/44 ,  H01L29/40

CPC classification number: H01L29/66507 ,  H01L21/28097

Abstract: A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

Abstract translation: 提供了在具有活性区域的基板上形成硅化栅的方法。 该方法包括在有源区和栅极的一部分上形成硅化物，留下栅极的剩余部分未被硅化; 在成形步骤之后在有源区和栅上形成屏蔽层; 在所述有源区上的所述屏蔽层的部分上形成涂层; 打开所述屏蔽层以暴露所述栅极，其中所述涂层在所述打开步骤期间保护所述屏蔽层的所述部分在所述有源区域上方; 在暴露的栅极上沉积金属层; 并退火以使金属与栅极反应，使栅极的剩余部分的至少一部分硅化。

公开(公告)号：US20050164503A1

公开(公告)日：2005-07-28

申请号：US10763688

申请日：2004-01-23

Applicant: Bor-Wen Chan ,  Baw-Ching Perng ,  Ying-Tsung Chen

Inventor： Bor-Wen Chan ,  Baw-Ching Perng ,  Ying-Tsung Chen

IPC: H01L21/28 ,  H01L21/302 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/461

CPC classification number: H01L29/66545 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/6656

Abstract: A method for forming an ultra narrow semiconductive gate structure utilizes a tapered hardmask covered by an oxide liner. The tapered hardmask is formed over the semiconductive gate material by tapered etching. After the tapered hardmask structure is formed over the semiconductive material, an oxide layer is formed over the tapered hardmask. A sequence of highly selective etch operations are carried out to etch uncovered portions of the semiconductive gate material while the portions of the gate material covered by the tapered hardmask and oxide film remain unetched to form ultra narrow gate structures.

Abstract translation: 用于形成超窄半导体栅极结构的方法利用由氧化物衬垫覆盖的锥形硬掩模。 通过锥形蚀刻在半导体栅极材料上形成锥形硬掩模。 在半导体材料上形成锥形硬掩模结构之后，在锥形硬掩模上形成氧化物层。 执行高选择性蚀刻操作的序列以蚀刻半导体栅极材料的未覆盖部分，同时由锥形硬掩模和氧化物膜覆盖的栅极材料的部分保持未蚀刻以形成超窄栅极结构。

公开(公告)号：US20050164478A1

公开(公告)日：2005-07-28

申请号：US10764913

申请日：2004-01-26

Applicant: Bor-Wen Chan ,  Yi-Chun Huang ,  Baw-Ching Perng ,  Hun-Jan Taq

Inventor： Bor-Wen Chan ,  Yi-Chun Huang ,  Baw-Ching Perng ,  Hun-Jan Taq

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234

CPC classification number: H01L21/28123 ,  H01L21/0271 ,  H01L21/0338 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/823437

Abstract: A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature having a width w1 in the top layer. A pattern transfer through the underlayer is performed with an anisotropic etch based on H2/N2 and SO2 chemistry. The feature formed in the bilayer stack is trimmed by 10 nm or more to a width w2 by a HBr/O2/Cl2 plasma etch. The pattern transfer through an underlying gate layer is performed with a third etch based on HBr/O2/Cl2 chemistry. The underlayer is stripped by an O2 ashing with no damage to the gate electrode. Excellent profile control of the gate electrode is achieved and a larger (w1−w2) is possible than in prior art methods.

Abstract translation: 描述了在MOSFET的栅电极制造期间修整光致抗蚀剂层的工艺。 在较厚的有机底层上具有顶部光致抗蚀剂层的双层叠层以193nm或157nm辐射图案曝光以形成顶层中具有宽度w 1 1的特征。 通过底层的图案转移通过基于H 2 N 2 N 2 N 2 SO 3和SO 2 H 2化学的各向异性蚀刻进行。 通过HBr / O 2 / Cl 2等离子体将形成在双层叠层中的特征修剪10nm以上至宽度w 2 2 <！ - SIPO

公开(公告)号：US06291312B1

公开(公告)日：2001-09-18

申请号：US09395108

申请日：1999-09-14

Applicant: Bor-Wen Chan ,  Yuan-Hung Liu

Inventor： Bor-Wen Chan ,  Yuan-Hung Liu

IPC: H01L2176

CPC classification number: H01L21/76224

Abstract: A method for forming a pullback opening above a shallow trench isolation structure. A patterned mask layer is formed over a substrate. A sacrificial layer is formed on the sidewalls of the mask layer. The exposed portion of the substrate is etched to form a trench in the substrate. The sacrificial layer is removed to increase the width of the opening above the trench.

Abstract translation: 一种用于在浅沟槽隔离结构上形成回拉开口的方法。 在衬底上形成图案化掩模层。 牺牲层形成在掩模层的侧壁上。 蚀刻衬底的暴露部分以在衬底中形成沟槽。 去除牺牲层以增加沟槽上方的开口的宽度。

公开(公告)号：US06232175B1

公开(公告)日：2001-05-15

申请号：US09466044

申请日：1999-12-17

Applicant: Yuan-Hung Liu ,  Bor-Wen Chan

Inventor： Yuan-Hung Liu ,  Bor-Wen Chan

IPC: H01L218242

CPC classification number: H01L28/92 ,  H01L21/32139 ,  H01L27/10852

Abstract: A double recess crown-shaped DRAM capacitor is formed in a simplified process. A dielectric layer is formed over a substrate. Using photolithographic and etching techniques, a contact opening is formed in the dielectric layer. A conductive layer is formed over the dielectric layer filling the contact opening to form a conductive plug. A second dielectric layer is formed over the conductive layer. Again using photolithographic and etching techniques, the second dielectric layer is patterned to form a trapezoidal-shaped dielectric layer. An organic bottom anti-reflective coating (organic BARC) is coated over the trapezoidal-shaped dielectric layer and the conductive layer. Organic BARC above the trapezoidal-shaped dielectric layer is removed. Using the organic BARC as an etching mask, the trapezoidal-shaped dielectric layer is etched to form triangular-shaped dielectric layers and a trench in the conductive layer. The residual organic BARC is completely removed. Using the triangular-shaped dielectric layers as a hard etching mask, two types of trenches each having a different depth are formed in the conductive layer. The triangular-shaped dielectric layers are removed to form a double-recess lower electrode. Hemispherical silicon grains are grown over the interior surface of the double-recess lower electrode as well as the external sidewalls. Finally, a conformal dielectric layer and a conformal conductive layer are sequentially formed over the surface of the double-recess lower electrode.

Abstract translation: 以简化的工艺形成双凹槽冠状DRAM电容器。 介电层形成在衬底上。 使用光刻和蚀刻技术，在电介质层中形成接触开口。 在填充接触开口的电介质层上形成导电层以形成导电插塞。 在导电层上形成第二介电层。 再次使用光刻和蚀刻技术，将第二介电层图案化以形成梯形介电层。 将有机底部抗反射涂层（有机BARC）涂覆在梯形介电层和导电层上。 去除梯形介电层上方的有机BARC。 使用有机BARC作为蚀刻掩模，蚀刻梯形介电层以在导电层中形成三角形介电层和沟槽。 残留的有机BARC被完全去除。 使用三角形介电层作为硬蚀刻掩模，在导电层中形成各具有不同深度的两种类型的沟槽。 去除三角形电介质层以形成双凹槽下电极。 半球状硅晶粒生长在双凹槽下电极的内表面以及外侧壁上。 最后，在双凹槽下电极的表面上依次形成保形电介质层和保形导电层。

公开(公告)号：US08841192B2

公开(公告)日：2014-09-23

申请号：US13444715

申请日：2012-04-11

Applicant: Tan-Chen Lee ,  Bor-Wen Chan

Inventor： Tan-Chen Lee ,  Bor-Wen Chan

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/456 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/7833 ,  H01L2924/0002

Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.

Abstract translation: 提供了具有改进的滚降电阻率和可靠性的半导体器件。 半导体器件包括覆盖半导体衬底的栅极电介质，覆盖栅极电介质的栅极电极，栅电极上的栅极硅化物区域，与栅极电介质相邻的源极/漏极区域，以及源极/漏极硅化物区域， 漏极区域，其中源极/漏极硅化物区域和栅极硅化物区域具有不同的金属组成。

公开(公告)号：US08564072B2

公开(公告)日：2013-10-22

申请号：US12753372

申请日：2010-04-02

Applicant: Bor-Wen Chan ,  Hsueh Wen Tsau

Inventor： Bor-Wen Chan ,  Hsueh Wen Tsau

IPC: H01L21/70

CPC classification number: H01L29/401 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/2855 ,  H01L21/67207 ,  H01L21/76846 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a blocking structure between a metal layer and at least one underlying layer. The blocking structure has a first layer configured for preventing diffusion of metal from the metal layer into the at least one underlying layer, and a second layer configured for enhancing electrical performance of the semiconductor device.

Abstract translation: 半导体器件包括在金属层和至少一个下层之间的阻挡结构。 阻挡结构具有被配置为防止金属从金属层扩散到至少一个下层中的第一层，以及被配置用于增强半导体器件的电性能的第二层。

公开(公告)号：US20110171820A1

公开(公告)日：2011-07-14

申请号：US12687714

申请日：2010-01-14

Applicant: Hsueh Wen Tsau ,  Kuang-Yuan Hsu ,  Bor-Wen Chan

Inventor： Hsueh Wen Tsau ,  Kuang-Yuan Hsu ,  Bor-Wen Chan

IPC: H01L21/28

CPC classification number: H01L21/28088 ,  H01L21/0228 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a substrate. A dummy gate is formed over the substrate. A dielectric material is formed around the dummy gate. The dummy gate is then removed to form an opening in the dielectric material. Thereafter, a work function metal layer is formed to partially fill the opening. The remainder of the opening is then filled with a conductive layer using one of a polysilicon substitute method and a spin coating method.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供基板。 在基板上形成虚拟栅极。 在虚拟栅极周围形成电介质材料。 然后去除伪栅极以在电介质材料中形成开口。 此后，形成功函数金属层以部分地填充开口。 然后使用多晶硅替代方法和旋涂方法之一用导电层填充开口的剩余部分。

公开(公告)号：US20110151655A1

公开(公告)日：2011-06-23

申请号：US12641560

申请日：2009-12-18

Applicant: Bor-Wen Chan ,  Hsueh Wen Tsau ,  Kuang-Yuan Hsu

Inventor： Bor-Wen Chan ,  Hsueh Wen Tsau ,  Kuang-Yuan Hsu

IPC: H01L21/28

CPC classification number: H01L29/7848 ,  H01L21/28079 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/495 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7834

Abstract: The present disclosure provides various methods of fabricating a semiconductor device. A method of fabricating a semiconductor device includes providing a semiconductor substrate and forming a gate structure over the substrate. The gate structure includes a first spacer and a second spacer formed apart from the first spacer. The gate structure also includes a dummy gate formed between the first and second spacers. The method also includes removing a portion of the dummy gate from the gate structure thereby forming a partial trench. Additionally, the method includes removing a portion of the first spacer and a portion of the second spacer adjacent the partial trench thereby forming a widened portion of the partial trench. In addition, the method includes removing a remaining portion of the dummy gate from the gate structure thereby forming a full trench. A high k film and a metal gate are formed in the full trench.

Abstract translation: 本公开提供制造半导体器件的各种方法。 制造半导体器件的方法包括提供半导体衬底并在衬底上形成栅极结构。 栅极结构包括第一间隔物和与第一间隔物分开形成的第二间隔物。 栅极结构还包括形成在第一和第二间隔物之间​​的虚拟栅极。 该方法还包括从栅极结构中去除伪栅极的一部分，从而形成部分沟槽。 此外，该方法包括移除第一间隔物的一部分和邻近部分沟槽的第二间隔物的一部分，从而形成部分沟槽的加宽部分。 此外，该方法包括从栅极结构中去除伪栅极的剩余部分，从而形成全沟槽。 在整个沟槽中形成高k膜和金属栅极。