公开(公告)号：US06475850B2

公开(公告)日：2002-11-05

申请号：US09873808

申请日：2001-06-04

申请人： Michael Violette ,  Martin Ceredig Roberts

发明人： Michael Violette ,  Martin Ceredig Roberts

IPC分类号： H01L218238

CPC分类号： H01L21/8249

摘要： A BiCMOS integrated circuit is fabricated using a minimum number of wafer processing steps and yet offers the IC circuit designer five (5) different transistor types. These types include P-channel and N-channel MOS transistors and three different bipolar transistors whose emitters are all formed by a different process and all are characterized by different current gains and different breakdown voltages. A differential silicon dioxide/silicon nitride masking technique is used in the IC fabrication process wherein both P-type buried layers (PBL) and N-type buried layers (NBL) are formed in a silicon substrate using a single mask set and further wherein P-type wells and N-type wells are formed above these buried layers in an epitaxial layer, also using a single SiO2/Si3N4 differential mask set. Two of the bipolar transistor emitters are formed by out diffusion from first and second levels of polysilicon, whereas the emitter of the third bipolar transistor is formed by ion implantation doping.

摘要翻译： 使用最少数量的晶圆处理步骤制造BiCMOS集成电路，并提供IC电路设计器五（5）种不同的晶体管类型。 这些类型包括P沟道和N沟道MOS晶体管以及三个不同的双极晶体管，其发射极都由不同的工艺形成，并且都以不同的电流增益和不同的击穿电压为特征。 在IC制造工艺中使用差示二氧化硅/氮化硅掩蔽技术，其中使用单个掩模组在硅衬底中形成P型掩埋层（PBL）和N型掩埋层（NBL），并且其中P 类型的阱和N型阱在外延层上形成在这些掩埋层上方，也使用单个SiO 2 / Si 3 N 4差分掩模集合。 两个双极晶体管发射极通过从第一和第二层多晶硅的扩散形成，而第三双极晶体管的发射极通过离子注入掺杂形成。

公开(公告)号：US06221711B1

公开(公告)日：2001-04-24

申请号：US09076324

申请日：1998-05-11

申请人： Martin Ceredig Roberts ,  Kunal R. Parekh

发明人： Martin Ceredig Roberts ,  Kunal R. Parekh

IPC分类号： H01L218242

CPC分类号： H01L21/76838 ,  H01L21/768 ,  H01L21/76802 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry are described. In one embodiment, a pair of conductive contact plugs are formed to project outwardly relative to a semiconductor wafer. The plugs have respective tops, one of which being covered with different first and second insulating materials. An opening is etched through one of the first and second insulating materials to expose only one of the tops of the pair of plugs. Electrically conductive material is formed within the opening and in electrical connection with the one plug. In a preferred embodiment, two-spaced apart conductive lines are formed over a substrate and conductive plugs are formed between, and on each side of the conductive lines. The conductive plug formed between the conductive lines provides a bit line contact plug having an at least partially exposed top portion. The exposed top portion is encapsulated with a first insulating material. A layer of second different insulating material is formed over the substrate. Portions of the second insulating material are removed selectively relative to the first insulating material over the conductive plugs on each side of the conductive lines to provide a pair of capacitor containers. Capacitors are subsequently formed in the containers.

摘要翻译： 描述了与导电插塞电接触的方法，形成接触开口的方法以及形成动态随机存取存储器电路的方法。 在一个实施例中，形成一对导电接触插塞相对于半导体晶片向外突出。 插头具有相应的顶部，其中一个顶部覆盖有不同的第一和第二绝缘材料。 通过第一绝缘材料和第二绝缘材料之一蚀刻开口以露出该对插头的顶部中的一个。 导电材料形成在开口内并与一个插头电连接。 在优选实施例中，在衬底上形成两个间隔开的导电线，并且在导电线的每一侧之间和之间形成导电插塞。 形成在导电线之间的导电插塞提供具有至少部分暴露的顶部的位线接触插头。 暴露的顶部用第一绝缘材料封装。 在衬底上形成第二不同绝缘材料层。 通过在导电线的每一侧上的导电插塞上相对于第一绝缘材料选择性地去除第二绝缘材料的部分，以提供一对电容器容器。 随后在容器中形成电容器。

公开(公告)号：US6103020A

公开(公告)日：2000-08-15

申请号：US971870

申请日：1997-11-19

申请人： Ceredig Roberts ,  Werner Juengling

发明人： Ceredig Roberts ,  Werner Juengling

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L29/12

CPC分类号： H01L21/32 ,  H01L21/76221

摘要： A field isolation process utilizes two or more isolation formation steps to form active areas on a semiconductor substrate. Each field isolation step forms a portion of the field isolation in a manner which reduces field oxide encroachment, in particular, by forming field oxide islands. The superposition of field isolation configurations define the desired active areas. A presently preferred dual-mask process may be carried out using a single masking stack, or more preferably using a masking stack for each isolation mask. The present isolation process further allows isolation features to be optimized for a variety of isolation requirements on the same integrated circuit.

摘要翻译： 场隔离过程利用两个或更多个隔离形成步骤在半导体衬底上形成有源区。 每个场隔离步骤以减少场氧化物侵蚀的方式形成场隔离的一部分，特别是通过形成场氧化物岛。 现场隔离配置的叠加定义了所需的有效区域。 目前优选的双掩模方法可以使用单个掩蔽叠层进行，或者更优选地使用用于每个隔离掩模的掩蔽堆叠。 本隔离过程进一步允许针对同一集成电路上的各种隔离要求进行优化的隔离特性。

公开(公告)号：US5985767A

公开(公告)日：1999-11-16

申请号：US228725

申请日：1999-01-12

申请人： Ceredig Roberts ,  Anand Srinivasan ,  Gurtej Sandhu ,  Sujit Sharan

发明人： Ceredig Roberts ,  Anand Srinivasan ,  Gurtej Sandhu ,  Sujit Sharan

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L21/00

CPC分类号： H01L21/76865 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L21/76844 ,  H01L2924/0002

摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer is deposited over an insulating layer, either before or after contact opening formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer overlying the contact lip while depositing material from the conductive layer into the lower corner of the contact, where coverage has traditionally been poor. A second conductive layer may then be deposited into the contact to supplement coverage provided by the first conductive layer and the facet etch.

摘要翻译： 公开了一种用于提供与导电材料，特别是金属的接触的改进的台阶覆盖的方法。 在接触开口形成之前或之后，在绝缘层上沉积导电层。 在导电层沉积和接触形成之后，进行小面蚀刻以使覆盖接触唇的导电层倾斜，同时将材料从导电层沉积到接触的下角，其中覆盖传统上较差。 然后可以将第二导电层沉积到接触中以补充由第一导电层提供的覆盖层和小面蚀刻。

公开(公告)号：US5844835A

公开(公告)日：1998-12-01

申请号：US815302

申请日：1997-03-11

申请人： Ceredig Roberts

发明人： Ceredig Roberts

IPC分类号： H01L27/11 ,  H01L27/02

CPC分类号： H01L27/1112 ,  Y10S257/903 ,  Y10S257/904

摘要： An SRAM cell having at least four field effect transistors includes, a) at least four transistor gates, a ground line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and b) the Vcc line and the ground line being provided in different respective elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates. In an additional aspect, an SRAM cell having at least four field effect transistors includes, i) at least four transistor gates, an electrical interconnect line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and ii) the Vcc line and the electrical interconnect line being provided in different respective is elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates.

摘要翻译： 具有至少四个场效应晶体管的SRAM单元包括：a）至少四个晶体管栅极，接地线，Vcc线和一对上拉电阻; 四个晶体管栅极具有可操作地与其相邻的晶体管扩散区域; 以及b）Vcc线和接地线设置在不同的各个正面中，所述上拉电阻在Vcc之间基本上垂直延伸，并且与所述栅极可操作地相邻的各个晶体管扩散区域选择。 在另一方面，具有至少四个场效应晶体管的SRAM单元包括：i）至少四个晶体管栅极，电互连线，Vcc线和一对上拉电阻; 四个晶体管栅极具有可操作地与其相邻的晶体管扩散区域; 以及ii）Vcc线和设置在不同的相互的电互连线是正面，所述上拉电阻在Vcc之间基本上垂直延伸，并且与所述栅极可操作地相邻的各个晶体管扩散区域选择。

公开(公告)号：US07368372B2

公开(公告)日：2008-05-06

申请号：US11386167

申请日：2006-03-21

申请人： Fred D. Fishburn ,  Martin Ceredig Roberts

发明人： Fred D. Fishburn ,  Martin Ceredig Roberts

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/8236

CPC分类号： H01L21/31053 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823828 ,  H01L21/823842 ,  Y10S438/941

摘要： The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate layer are patterned and etched to form a first set of conductive gate constructions over the substrate. A dielectric material is formed and planarized over the first set of gate constructions. Thereafter, the insulative capping layer and the conductive gate layer are patterned and etched to form a second set of conductive gate constructions over the substrate. Other aspects and implementations are contemplated.

摘要翻译： 本发明包括制造多组场效应晶体管的方法。 在一个实施方案中，在绝缘覆盖层上形成蚀刻停止层，所述绝缘覆盖层形成在形成在衬底上的导电栅极层上。 蚀刻停止层，绝缘覆盖层和导电栅极层被图案化和蚀刻以在衬底上形成第一组导电栅极结构。 在第一组栅极结构上形成并平坦化介电材料。 此后，对绝缘覆盖层和导电栅极层进行构图和蚀刻，以在衬底上形成第二组导电栅极结构。 考虑了其他方面和实现。

公开(公告)号：US20060017074A1

公开(公告)日：2006-01-26

申请号：US11217998

申请日：2005-09-01

申请人： Pary Baluswamy ,  Scott DeBoer ,  Ceredig Roberts ,  Tim Bossart

发明人： Pary Baluswamy ,  Scott DeBoer ,  Ceredig Roberts ,  Tim Bossart

IPC分类号： H01L27/148

CPC分类号： G03F7/70633 ,  H01L22/34 ,  Y10S438/975

摘要： The present invention includes a residue-free overlay target, as well as a method of forming a residue-free overlay target. The residue-free overlay target of the present invention is defined by trenches or pads including a series of raised lines. The raised lines included in the overlay target of the present invention substantially eliminate any surface topography, such as depressions, at the top surface of overlying material layers and, thereby, prevent accumulation of process residue which may obscure the overlay target and inhibit further processing. The method of the present invention may be accomplished and modified using process technology known in the semiconductor fabrication art and includes providing a semiconductor substrate, depositing a resist layer, patterning the resist, and executing a wet or dry etch to create at least one overlay target according to the present invention.

摘要翻译： 本发明包括无残留覆盖靶，以及形成无残留覆盖靶的方法。 本发明的无残留覆盖靶由包括一系列凸起线的沟槽或焊盘限定。 包括在本发明的覆盖目标物中的凸起线实质上消除了在覆盖材料层的顶表面上的任何表面形貌，例如凹陷，并且因此防止可能掩盖覆盖目标并阻止进一步处理的工艺残余物的累积。 可以使用半导体制造领域中已知的工艺技术来实现和修改本发明的方法，并且包括提供半导体衬底，沉积抗蚀剂层，图案化抗蚀剂，以及执行湿法或干蚀刻以产生至少一个覆盖靶 根据本发明。

公开(公告)号：US06914017B1

公开(公告)日：2005-07-05

申请号：US09651790

申请日：2000-08-30

申请人： Pary Baluswamy ,  Scott J. DeBoer ,  Ceredig Roberts ,  Tim H. Bossart

发明人： Pary Baluswamy ,  Scott J. DeBoer ,  Ceredig Roberts ,  Tim H. Bossart

IPC分类号： G03F7/20 ,  H01L21/302

CPC分类号： G03F7/70633 ,  H01L22/34 ,  Y10S438/975

摘要： The present invention includes a residue-free overlay target, as well as a method of forming a residue-residue free overlay target. The residue-free overlay target of the present invention is defined by trenches or pads including a series of raised lines. The raised lines included in the overlay target of the present invention substantially eliminate any surface topography, such as depressions, at the top surface of overlying material layers, and, thereby, prevent accumulation of process residue which may obscure the overlay target and inhibit further processing. The method of the present invention may be accomplished and modified using process technology known in the semiconductor fabrication art and includes providing a semiconductor substrate, depositing a resist layer, patterning the resist, and executing a wet or dry etch to create at least one overlay target according to the present invention.

摘要翻译： 本发明包括无残留覆盖靶，以及形成无残留覆盖靶的方法。 本发明的无残留覆盖靶由包括一系列凸起线的沟槽或焊盘限定。 包括在本发明的覆盖靶中的突起线基本上消除了覆盖材料层的顶表面处的任何表面形貌，例如凹陷，并且因此防止可能掩盖覆盖靶并阻止进一步加工的工艺残留物的堆积 。 可以使用半导体制造领域中已知的工艺技术来实现和修改本发明的方法，并且包括提供半导体衬底，沉积抗蚀剂层，图案化抗蚀剂，以及执行湿法或干蚀刻以产生至少一个覆盖靶 根据本发明。

公开(公告)号：US20050070069A1

公开(公告)日：2005-03-31

申请号：US10992549

申请日：2004-11-18

申请人： Pary Baluswamy ,  Scott DeBoer ,  Ceredig Roberts ,  Tim Bossart

发明人： Pary Baluswamy ,  Scott DeBoer ,  Ceredig Roberts ,  Tim Bossart

IPC分类号： G03F7/20 ,  H01L21/76

CPC分类号： G03F7/70633 ,  H01L22/34 ,  Y10S438/975

摘要： The present invention includes a residue-free overlay target, as well as a method of forming a residue-free overlay target. The residue-free overlay target of the present invention is defined by trenches or pads including a series of raised lines. The raised lines included in the overlay target of the present invention substantially eliminate any surface topography, such as depressions, at the top surface of overlying material layers and, thereby, prevent accumulation of process residue which may obscure the overlay target and inhibit further processing. The method of the present invention may be accomplished and modified using process technology known in the semiconductor fabrication art and includes providing a semiconductor substrate, depositing a resist layer, patterning the resist, and executing a wet or dry etch to create at least one overlay target according to the present invention.

摘要翻译： 本发明包括无残留覆盖靶，以及形成无残留覆盖靶的方法。 本发明的无残留覆盖靶由包括一系列凸起线的沟槽或焊盘限定。 包括在本发明的覆盖目标物中的凸起线实质上消除了在覆盖材料层的顶表面上的任何表面形貌，例如凹陷，并且因此防止可能掩盖覆盖目标并阻止进一步处理的工艺残余物的累积。 可以使用半导体制造领域中已知的工艺技术来实现和修改本发明的方法，并且包括提供半导体衬底，沉积抗蚀剂层，图案化抗蚀剂，以及执行湿法或干蚀刻以产生至少一个覆盖靶 根据本发明。

公开(公告)号：US06800517B2

公开(公告)日：2004-10-05

申请号：US10792532

申请日：2004-03-02

申请人： Gurtej S. Sandhu ,  Trung Tri Doan ,  Howard E. Rhodes ,  Sujit Sharan ,  Philip J. Ireland ,  Martin Ceredig Roberts

发明人： Gurtej S. Sandhu ,  Trung Tri Doan ,  Howard E. Rhodes ,  Sujit Sharan ,  Philip J. Ireland ,  Martin Ceredig Roberts

IPC分类号： H01L218238

CPC分类号： H01L21/76877 ,  H01L21/28518

摘要： The invention includes a method of forming a conductive interconnect. An electrical node location is defined to be supported by a silicon-containing substrate. A silicide is formed in contact with the electrical node location. The silicide is formed by exposing the substrate to hydrogen, TiCl4 and plasma conditions to cause Ti from the TiCl4 to combine with silicon of the substrate to form TiSix. Conductively doped silicon material is formed over the silicide. The conductively doped silicon material is exposed to one or more temperatures of at least about 800° C. The silicide is also exposed to the temperatures of at least about 800° C.