公开(公告)号：US20060270144A1

公开(公告)日：2006-11-30

申请号：US11499348

申请日：2006-08-03

Applicant: Cheng-Chih Huang

Inventor： Cheng-Chih Huang

IPC: H01L21/8244 ,  H01L29/00

CPC classification number: H01L27/10876 ,  H01L27/10841

Abstract: Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The first conductive layer is isolated the substrate by a collar dielectric layer. A trench top oxide (TTO) layer is disposed on the first conductive layer. A vertical transistor is disposed over the TTO layer. The vertical transistor comprises a gate dielectric layer disposed on the sidewalls of the upper portion of the trench, and a metal gate disposed in the upper portion of the trench.

Abstract translation: 具有垂直晶体管和电容器的存储单元及其制造方法。 存储单元包括具有沟槽的衬底。 电容器设置在沟槽的底部。 第一导电层电耦合到电容器。 第一导电层通过套环电介质层隔离衬底。 沟槽顶部氧化物（TTO）层设置在第一导电层上。 垂直晶体管设置在TTO层上。 垂直晶体管包括设置在沟槽上部侧壁上的栅介电层和设置在沟槽上部的金属栅极。

公开(公告)号：US07078748B2

公开(公告)日：2006-07-18

申请号：US10865763

申请日：2004-06-14

Applicant: Matthias Goldbach ,  Frank Jakubowski ,  Ralf Koepe ,  Chao-Wen Lay ,  Kristin Schupke ,  Michael Schmidt ,  Cheng-Chih Huang

Inventor： Matthias Goldbach ,  Frank Jakubowski ,  Ralf Koepe ,  Chao-Wen Lay ,  Kristin Schupke ,  Michael Schmidt ,  Cheng-Chih Huang

IPC: H01L27/148

CPC classification number: H01L21/28044

Abstract: A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a transition metal interface layer, a nitride barrier layer and then a metal layer on a gate dielectric, wherein the transition metal is titanium, tantalum or cobalt. Patterning the gate electrode layer stack comprises a step of patterning the metal layer and the barrier layer with an etch stop on the surface of the interface layer. Exposed portions of the interface layer are removed and the remaining portions are pulled back from the sidewalls of the gate stack structure leaving divots extending along the sidewalls of the gate stack structure between the barrier layer and the polysilicon layer. A nitride liner encapsulating the metal layer, the barrier layer and the interface layer fills the divots left by the pulled-back interface layer. The nitride liner is opened before the polysilicon layer is patterned. As the requirement for an overetch into the polysilicon layer during the etch of the metal layer, the barrier layer and the interface layer is omitted, the height of the polysilicon layer can be reduced. The aspect ration of the gate stack structure is improved, the feasibility of pattern and fill processes enhanced and the range of an angle under which implants can be performed is extended.

Abstract translation: 通过提供具有多晶硅层，过渡金属界面层，氮化物阻挡层，然后在栅极电介质上的金属层的栅电极层堆叠来制造场效应晶体管器件的多层栅极堆叠结构，其中， 过渡金属是钛，钽或钴。 对栅电极层堆叠进行图案化包括在界面层的表面上用蚀刻阻挡层图案化金属层和阻挡层的步骤。 界面层的暴露部分被去除，其余的部分从栅极叠层结构的侧壁被拉回，留下在阻挡层和多晶硅层之间的栅堆叠结构的侧壁延伸的纹理。 封装金属层，阻挡层和界面层的氮化物衬垫填充由拉回界面层留下的凹坑。 在将多晶硅层图案化之前打开氮化物衬垫。 作为在金属层的蚀刻期间进行多晶硅层的蚀刻的要求，省略了阻挡层和界面层，可以降低多晶硅层的高度。 提高了栅极堆叠结构的方面，增加了图案和填充过程的可行性，并且延长了可以进行植入的角度范围。

公开(公告)号：US06773993B2

公开(公告)日：2004-08-10

申请号：US09880783

申请日：2001-06-15

Applicant: Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

IPC: H01L21336

CPC classification number: H01L29/42332 ,  H01L21/28273

Abstract: A method for manufacturing a split-gate flash memory cell, comprising the steps of forming an active region on a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a first dielectric layer on the buffer layer; removing part of the first dielectric layer; defining an opening; removing the buffer layer within the opening; forming a gate insulating layer and floating gates; forming a source region in the semiconductor substrate; depositing a conformal second dielectric layer on the opening; removing the buffer layer outside the first dielectric layer and the floating gates; and forming an oxide layer and control gates.

公开(公告)号：US20110140196A1

公开(公告)日：2011-06-16

申请号：US12635662

申请日：2009-12-10

Applicant: Shing-Hwa Renn ,  Cheng-Chih Huang ,  Yung-Meng Huang

Inventor： Shing-Hwa Renn ,  Cheng-Chih Huang ,  Yung-Meng Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/336

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10885

Abstract: An embedded bit line structure, in which, a substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer, and a bit line is disposed within the lower portion of the trench along one side of an active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.

Abstract translation: 一种嵌入式位线结构，其中，衬底包括具有原始顶表面的绝缘体层和在绝缘体层的原始顶表面上的半导体层，并且位线沿着一侧设置在沟槽的下部 的活跃区域。 位线包括第一部分和第二部分。 第一部分位于绝缘体层内并且位于绝缘体层的原始顶表面下方。 第二部分设置在第一部分上以电连接有源区的半导体层。 绝缘体衬垫设置在位线的第一部分上，位于位线的第二部分与衬底的半导体层之间，与激活区域相反以进行隔离。 STI设置在沟槽内以围绕有源区域进行隔离。

公开(公告)号：US07074700B2

公开(公告)日：2006-07-11

申请号：US10943699

申请日：2004-09-17

Applicant: Cheng-Chih Huang ,  Sheng-Wei Yang ,  Chen-Chou Huang ,  Sheng-Tsung Chen

Inventor： Cheng-Chih Huang ,  Sheng-Wei Yang ,  Chen-Chou Huang ,  Sheng-Tsung Chen

IPC: H01L21/22

CPC classification number: H01L27/10864 ,  H01L27/10867 ,  H01L27/10876

Abstract: A method for forming isolation layer in a vertical DRAM. A semiconductor substrate with a plurality of first trenches is provided, with a collar dielectric layer is formed on a sidewall of each, and each filled with a first conducting layer. A patterned mask layer is formed on the semiconductor substrate, and the semiconductor substrate is etched using the patterned mask layer as an etching mask to form a plurality of second trenches. The patterned mask layer is removed. Each second trench is filled with an insulating layer acting as an isolation. Each of first conducting layers is etched to form a plurality of grooves. A doped area acting as a buried strap is formed in the semiconductor substrate beside each groove. A trench top insulating layer is formed in the bottom surface of each trench. Each first trench is filled with a second conducting layer acting as a gate.

Abstract translation: 一种用于在垂直DRAM中形成隔离层的方法。 提供了具有多个第一沟槽的半导体衬底，其中，在每个的侧壁上形成一个环形电介质层，并且各自填充有第一导电层。 在半导体衬底上形成图案化掩模层，并使用图案化掩模层作为蚀刻掩模蚀刻半导体衬底，以形成多个第二沟槽。 去除图案化的掩模层。 每个第二沟槽填充有用作隔离层的绝缘层。 每个第一导电层被蚀刻以形成多个凹槽。 在每个沟槽旁边的半导体衬底中形成用作掩埋带的掺杂区域。 沟槽顶部绝缘层形成在每个沟槽的底表面中。 每个第一沟槽填充有用作栅极的第二导电层。

公开(公告)号：US20050124111A1

公开(公告)日：2005-06-09

申请号：US10846321

申请日：2004-05-14

Applicant: Cheng-Chih Huang ,  Sheng-Wei Yang ,  Neng-Tai Shih ,  Chen-Chou Huang

Inventor： Cheng-Chih Huang ,  Sheng-Wei Yang ,  Neng-Tai Shih ,  Chen-Chou Huang

IPC: H01L21/02 ,  H01L21/8242 ,  H01L21/8238 ,  H01L21/20 ,  H01L21/8234 ,  H01L21/8244

CPC classification number: H01L28/40 ,  H01L27/10864 ,  H01L27/10867

Abstract: A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided. A collar dielectric layer is conformally formed on the trench bottom portion, and the trench is filled with a conducting layer. The collar dielectric layer is etched below the level of the surface of the conducting layer to form a groove between the conducting layer and the trench. The groove is filled with a doped conducting layer. The dopant in the doped conducting layer is diffused to the semiconductor substrate in an ion diffusion area as a buried strap. The conducting layer and the doped conducting layer are etched below the ion diffusion area. A top trench insulating layer is formed on the bottom of the trench, wherein the top trench insulating layer is lower than the ion diffusion area.

公开(公告)号：US06897108B2

公开(公告)日：2005-05-24

申请号：US10604361

申请日：2003-07-14

Applicant: Sheng-Wei Yang ,  Cheng-Chih Huang ,  Chien-Mao Liao

Inventor： Sheng-Wei Yang ,  Cheng-Chih Huang ,  Chien-Mao Liao

IPC: H01L21/3105 ,  H01L21/311 ,  H01L21/316 ,  H01L21/8242 ,  H01L21/20

CPC classification number: H01L27/10894 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31612 ,  H01L27/10864

Abstract: The present invention provides a process for planarizing array top oxide (ATO) in vertical MOSFET DRAM arrays. In contrast to the prior art ARC-RIE planarization method for EA/ES (etch array/etch support) module, the present invention takes advantage of chemical mechanical polishing (CMP) technique to overcome residue problems that used to occur at the transition region or array edge. It might cause capacitor device failure when ATO residue is left on the transition region.

Abstract translation: 本发明提供了一种在垂直MOSFET DRAM阵列中平面化阵列顶部氧化物（ATO）的方法。 与用于EA / ES（蚀刻阵列/蚀刻支持）模块的现有技术的ARC-RIE平面化方法相反，本发明利用化学机械抛光（CMP）技术来克服在过渡区域发生的残留问题， 阵列边缘。 当ATO残留物留在过渡区域时，可能会导致电容器故障。

公开(公告)号：US06794250B2

公开(公告)日：2004-09-21

申请号：US10449296

申请日：2003-05-29

Applicant: Ming Cheng Chang ,  Cheng-Chih Huang ,  Jeng-Ping Lin

Inventor： Ming Cheng Chang ,  Cheng-Chih Huang ,  Jeng-Ping Lin

IPC: H01L218247

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7881

Abstract: A vertical split gate flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, a tunnel layer, a first doping region, and a second doping region. The floating gate is disposed in the lower portion of the trench and insulated from the adjacent substrate by a floating gate oxide layer. The control gate is disposed over the floating gate and insulated from the adjacent substrate by a control gate oxide layer. The inter-gate dielectric layer is disposed between the floating gate and the control gate for insulation of the floating gate and the control gaze. The first doping region is formed in the substrate adjacent to the control gate and the second doping region is formed in the substrate below the first doping region and adjacent to the control gate to serve as source and drain regions with the first doping region.

Abstract translation: 垂直分闸门闪存单元。 存储单元包括衬底，浮置栅极，控制栅极，隧道层，第一掺杂区域和第二掺杂区域。 浮动栅极设置在沟槽的下部，并通过浮栅氧化层与相邻衬底绝缘。 控制栅极设置在浮置栅极上并通过控制栅极氧化物层与相邻衬底绝缘。 栅极间电介质层设置在浮置栅极和控制栅极之间，用于浮动栅极和控制注视的绝缘。 第一掺杂区域形成在与控制栅极相邻的衬底中，并且第二掺杂区域形成在第一掺杂区域下方的衬底中并且与控制栅极相邻，以用作具有第一掺杂区域的源极和漏极区域。