公开(公告)号：US20120322246A1

公开(公告)日：2012-12-20

申请号：US13162813

申请日：2011-06-17

Applicant: Sheng-Hsiung WANG ,  Hsien-Chin LIN ,  Yuan-Ching PENG ,  Chia-Pin LIN ,  Fan-Yi HSU ,  Ya-Jou HSIEH

Inventor： Sheng-Hsiung WANG ,  Hsien-Chin LIN ,  Yuan-Ching PENG ,  Chia-Pin LIN ,  Fan-Yi HSU ,  Ya-Jou HSIEH

IPC: H01L21/20 ,  H01L21/311 ,  H01L21/3205

CPC classification number: H01L21/823857 ,  H01L21/823842 ,  H01L29/66545

Abstract: A method for manufacturing the integrated circuit device including, providing a substrate having a first region and a second region. Forming a dielectric layer over the substrate in the first region and the second region. Forming a sacrificial gate layer over the dielectric layer. Patterning the sacrificial gate layer and the dielectric layer to form gate stacks in the first and second regions. Forming an ILD layer within the gate stacks in the first and second regions. Removing the sacrificial gate layer in the first and second regions. Forming a protector over the dielectric layer in the first region; and thereafter removing the dielectric layer in the second region.

Abstract translation: 一种用于制造集成电路器件的方法，包括提供具有第一区域和第二区域的衬底。 在第一区域和第二区域中的衬底上形成介电层。 在电介质层上形成牺牲栅极层。 对牺牲栅极层和电介质层进行图案化以在第一和第二区域中形成栅极叠层。 在第一和第二区域内的栅堆叠内形成ILD层。 去除第一和第二区域中的牺牲栅极层。 在第一区域中的介电层上形成保护膜; 然后除去第二区域中的电介质层。

公开(公告)号：US20120319192A1

公开(公告)日：2012-12-20

申请号：US13599507

申请日：2012-08-30

Applicant: Peng-Soon Lim ,  Chia-Pin Lin ,  Kuang-Yuan Hsu

Inventor： Peng-Soon Lim ,  Chia-Pin Lin ,  Kuang-Yuan Hsu

IPC: H01L27/092 ,  H01L27/088

CPC classification number: H01L27/092 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: An apparatus includes a first device. The first device includes a first projection and a first gate structure, the first projection extending upwardly from a substrate and having a first channel region therein, and the first gate structure engaging the first projection adjacent the first channel region. The first structure includes an opening over the first channel region, and a conformal, pure metal with a low resistivity disposed in the opening. The apparatus also includes a second device that includes a second projection and a second gate structure, the second projection extending upwardly from the substrate and having a second channel region therein, and the second gate structure engaging the second projection adjacent the second channel region. The second structure includes a silicide disposed over the second channel region, wherein the silicide includes a metal that is the same metal disposed in the opening.

Abstract translation: 一种装置包括第一装置。 第一装置包括第一突起和第一栅极结构，第一突起从衬底向上延伸并且在其中具有第一沟道区域，并且第一栅极结构接合与第一沟道区相邻的第一突起。 第一结构包括在第一通道区域上的开口，以及设置在开口中的具有低电阻率的保形的纯金属。 该装置还包括第二装置，其包括第二突起和第二栅极结构，第二突起从基板向上延伸并且在其中具有第二通道区域，并且第二栅极结构接合与第二通道区域相邻的第二突出部。 第二结构包括设置在第二通道区域上的硅化物，其中硅化物包括设置在开口中的相同金属的金属。

公开(公告)号：US08218282B2

公开(公告)日：2012-07-10

申请号：US12618074

申请日：2009-11-13

Applicant: Chia-Pin Lin

Inventor： Chia-Pin Lin

IPC: H01C7/12 ,  H02H3/20 ,  H02H3/22 ,  H02H9/00 ,  H03G11/00

CPC classification number: G11B20/10527 ,  G11B27/36 ,  H01L27/0248

Abstract: A portable electronic device includes an audio file playing unit and a surge protector device connected to the audio file playing unit. The surge protector device includes a protector module connected to an audio file playing unit and a processor module connected to the protector module and the audio file playing unit. The processor module detects electric surges in the audio file playing unit and controls the protector module to filter the detected electric surges when the audio file playing unit plays audio files.

Abstract translation: 便携式电子设备包括音频文件播放单元和连接到音频文件播放单元的浪涌保护器设备。 浪涌保护器装置包括连接到音频文件播放单元的保护器模块和连接到保护器模块和音频文件播放单元的处理器模块。 处理器模块检测音频文件播放单元中的电涌，并且当音频文件播放单元播放音频文件时，控制保护模块过滤检测到的电涌。

公开(公告)号：US20120015493A1

公开(公告)日：2012-01-19

申请号：US13241014

申请日：2011-09-22

Applicant: Chia-Pin Lin ,  Wen-Sheh Huang ,  Tian-Choy Gan ,  Chia-Lung Hung ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

Inventor： Chia-Pin Lin ,  Wen-Sheh Huang ,  Tian-Choy Gan ,  Chia-Lung Hung ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

IPC: H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/66803

Abstract: Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiNx or SiCNx and the second nitride film is SiCNx. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.

Abstract translation: 提供了形成在半导体鳍上的高k金属栅极结构。 在栅极结构和半导体鳍片上形成氮化物层，使用两个单独的沉积操作，首先形成非常薄的氮化物膜。 植入操作可以在两个氮化物膜沉积操作之间进行。 第一氮化物膜可以是SiNx或SiCNx，第二氮化物膜是SiCNx。 可以将氮化物膜组合以形成低湿蚀刻速率间隔物，使得能够进行进一步的处理操作而不损坏下面的结构，而不需要形成另外的虚设间隔物。 进一步的处理操作包括外延硅/ SiGe处理序列和用低蚀刻速率间隔物完整地进行的源极/漏极注入操作。

公开(公告)号：US20110210393A1

公开(公告)日：2011-09-01

申请号：US12714796

申请日：2010-03-01

Applicant: Hung-Kai Chen ,  Hsien-Hsin Lin ,  Chia-Pin Lin ,  Chien-Tai Chan ,  Yuan-Ching Peng

Inventor： Hung-Kai Chen ,  Hsien-Hsin Lin ,  Chia-Pin Lin ,  Chien-Tai Chan ,  Yuan-Ching Peng

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/336

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step.

Abstract translation: 一种方法包括形成在半导体衬底之上延伸的第一鳍片和第二鳍片，在它们之间具有浅沟槽隔离（STI）区域。 在STI区域的顶表面之上的第一和第二鳍之间限定空间。 第一高度限定在STI区域的顶表面和第一鳍片和第二鳍片的顶表面之间。 可流动的电介质材料沉积到该空间中。 电介质材料具有在STI区域的顶表面上方的顶表面，以便在介电材料的顶表面和第一和第二鳍片的顶表面之间限定第二高度。 第二个高度小于第一个高度。 在沉积步骤之后，第一和第二鳍片延伸部分别外延形成在电介质上方，分别在第一和第二鳍片上。

公开(公告)号：US20110019156A1

公开(公告)日：2011-01-27

申请号：US12789872

申请日：2010-05-28

Applicant: Chih-Chung Chang ,  Chia-Pin Lin ,  Yung-Chu Lin ,  Hsin-Mao Chung

Inventor： Chih-Chung Chang ,  Chia-Pin Lin ,  Yung-Chu Lin ,  Hsin-Mao Chung

IPC: G03B21/14 ,  G03B21/00

CPC classification number: H04N9/3179 ,  H04N9/3173

Abstract: A projection system and a method thereof are provided. The projection method includes the following steps. First, a processing module of an electronic device acquires a process ID of an application program via an operating system of the electronic device. Next, the processing module extracts display data corresponding to a window of the application program from a frame buffer of the electronic device stepwise with a predetermined frequency. Next, the processing module produces a plurality of pictures based on the extracted display data with the predetermined frequency. Next, the processing module transmits the pictures to a projector according to a predetermined transmission protocol. Finally, the projector projects the pictures sequentially.

Abstract translation: 提供一种投影系统及其方法。 该投影方法包括以下步骤。 首先，电子设备的处理模块经由电子设备的操作系统获取应用程序的处理ID。 接下来，处理模块以预定频率逐步从电子设备的帧缓冲器提取对应于应用程序的窗口的显示数据。 接下来，处理模块基于提取的具有预定频率的显示数据产生多个图像。 接下来，处理模块根据预定的传输协议将图像发送到投影仪。 最后，投影机依次投影图片。

公开(公告)号：US20090276491A1

公开(公告)日：2009-11-05

申请号：US12385899

申请日：2009-04-23

Applicant: Chia-Pin Lin ,  Yuan-Shu Hsiao

Inventor： Chia-Pin Lin ,  Yuan-Shu Hsiao

IPC: G06F15/16

CPC classification number: H04L67/025 ,  H04L67/14 ,  H04L67/145

Abstract: A management method for a remote digital signage provides communication between a web server and the digital signage to make the web server collect a system information from the digital signage. The management method includes the steps of: transmitting a heartbeat every period to the web server by the digital signage; receiving the heartbeat to transmit a reply signal to the digital signage by the web server, wherein the reply signal includes a command; receiving the reply signal to execute the command, and to transmit the system information to the web server by the digital signage; and receiving and storing the system information by the web server.

Abstract translation: 用于远程数字标牌的管理方法提供了Web服务器和数字标牌之间的通信，以使得Web服务器从数字标牌收集系统信息。 管理方法包括以下步骤：通过数字标牌将每个周期的心跳发送到web服务器; 接收所述心跳以由所述web服务器向所述数字标牌发送应答信号，其中所述应答信号包括命令; 接收所述应答信号以执行所述命令，并且通过所述数字标牌将所述系统信息发送到所述Web服务器; 并由web服务器接收和存储系统信息。

公开(公告)号：US08759943B2

公开(公告)日：2014-06-24

申请号：US12900626

申请日：2010-10-08

Applicant: Chih-Hung Tseng ,  Da-Wen Lin ,  Chien-Tai Chan ,  Chia-Pin Lin ,  Li-Wen Weng ,  An-Shen Chang ,  Chung-Cheng Wu

Inventor： Chih-Hung Tseng ,  Da-Wen Lin ,  Chien-Tai Chan ,  Chia-Pin Lin ,  Li-Wen Weng ,  An-Shen Chang ,  Chung-Cheng Wu

IPC: H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/7853

Abstract: A transistor includes a notched fin covered under a shallow trench isolation layer. One or more notch may be used, the size of which may vary along a lateral direction of the fin. In some embodiments, The notch is formed using anisotropic wet etching that is selective according to silicon orientation. Example wet etchants are tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH).

Abstract translation: 晶体管包括覆盖在浅沟槽隔离层下面的切口鳍。 可以使用一个或多个凹口，其尺寸可以沿翅片的横向方向变化。 在一些实施例中，使用根据硅取向选择性的各向异性湿蚀刻形成凹口。 实例湿蚀刻剂是氢氧化四甲基铵（TMAH）或氢氧化钾（KOH）。

公开(公告)号：US08362572B2

公开(公告)日：2013-01-29

申请号：US12711690

申请日：2010-02-24

Applicant: Chih-Hsiang Huang ,  Chia-Pin Lin

Inventor： Chih-Hsiang Huang ,  Chia-Pin Lin

IPC: H01L29/66

CPC classification number: H01L21/76224 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7853

Abstract: An integrated circuit device includes a gate region extending above a semiconductor substrate and extending in a first longitudinal direction. A first fin has a first sidewall that extends in a second longitudinal direction above the semiconductor substrate such that the first fin intersects the gate region. A second fin has a second sidewall extending in the second direction above the semiconductor substrate such that the second fin intersects the gate region. A shallow trench isolation (STI) region is formed in the semiconductor substrate between the first and second sidewalls of the first and second fins. A conductive layer disposed over the first insulating layer and over top surfaces of the first and second fins. A first insulating layer is disposed between an upper surface of the STI region and a lower surface of the conductive layer to separate the STI region from the conductive layer.

Abstract translation: 集成电路器件包括在半导体衬底上延伸并在第一纵向方向上延伸的栅极区域。 第一翅片具有第一侧壁，其在半导体衬底上方的第二纵向方向上延伸，使得第一鳍片与栅极区域相交。 第二鳍片具有在半导体衬底上方的第二方向上延伸的第二侧壁，使得第二鳍片与栅极区域相交。 在第一和第二鳍片的第一和第二侧壁之间的半导体衬底中形成浅沟槽隔离（STI）区域。 布置在所述第一绝缘层之上和所述第一和第二鳍片的顶表面之上的导电层。 第一绝缘层设置在STI区的上表面和导电层的下表面之间，以将STI区与导电层分离。

公开(公告)号：US20110248348A1

公开(公告)日：2011-10-13

申请号：US12756662

申请日：2010-04-08

Applicant: Tian-Choy Gan ,  Hsien-Chin Lin ,  Chia-Pin Lin ,  Shyue-Shyh Lin ,  Li-Shiun Chen ,  Shin Hsien Liao

Inventor： Tian-Choy Gan ,  Hsien-Chin Lin ,  Chia-Pin Lin ,  Shyue-Shyh Lin ,  Li-Shiun Chen ,  Shin Hsien Liao

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/8238 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including first and second poly gates, forming an inter-level dielectric (ILD) over the substrate, performing a chemical mechanical polishing on the ILD to expose the first and second poly gates, forming a mask to protect the first poly gate of the first gate structure, removing the second poly gate thereby forming a first trench, removing the mask, partially removing the first poly gate thereby forming a second trench, forming a work function metal layer partially filling the first and second trenches, forming a fill metal layer filling a remainder of the first and second trenches, and removing the metal layers outside the first and second trenches.

Abstract translation: 提供一种制造半导体器件的方法，该半导体器件包括在衬底的第一和第二区域上形成第一和第二鳍片，在第一和第二鳍片上形成第一和第二栅极结构，第一和第二栅极结构包括第一和第二多晶硅栅极 ，在所述衬底上形成层间电介质（ILD），在所述ILD上进行化学机械抛光以暴露所述第一和第二多晶硅栅极，形成掩模以保护所述第一栅极结构的所述第一多晶硅栅极， 从而形成第一沟槽，去除掩模，部分地移除第一多晶硅栅极，从而形成第二沟槽，形成部分填充第一和第二沟槽的功函数金属层，形成填充第一和第二沟槽的剩余部分的填充金属层 沟槽，并且去除第一和第二沟槽外的金属层。