公开(公告)号：US08054105B2

公开(公告)日：2011-11-08

申请号：US12639009

申请日：2009-12-16

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： G11C27/02 ,  H03K5/00 ,  H03K17/00

CPC分类号： G11C27/026 ,  H03M1/1295

摘要： A sample hold circuit and a method for sampling and holding a signal are provided. The sample hold circuit includes a sample unit, a direct current (DC) voltage elimination unit, and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an input signal, and the DC voltage elimination unit lowers a predetermined percentage of the DC voltage in the input signal sampled by the sample unit. When the sample hold circuit is in a second state, the DC voltage elimination unit eliminates the residual percentage of the DC voltage, and the hold unit outputs the alternating current (AC) signal in the input signal sampled by the sample unit.

摘要翻译： 提供了采样保持电路和采样和保持信号的方法。 采样保持电路包括采样单元，直流（DC）电压消除单元和保持单元。 当采样保持电路处于第一状态时，采样单元对输入信号进行采样，直流电压消除单元降低由采样单元采样的输入信号中的直流电压的预定百分比。 当采样保持电路处于第二状态时，直流电压消除单元消除直流电压的剩余百分比，并且保持单元输出由采样单元采样的输入信号中的交流（AC）信号。

公开(公告)号：US07969204B1

公开(公告)日：2011-06-28

申请号：US12642875

申请日：2009-12-21

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： G11C27/02

CPC分类号： H03M1/129 ,  G11C27/026 ,  H03M1/12

摘要： A sample hold circuit and a method for eliminating the offset voltage of the analog signal are provided. The sample hold circuit includes a sample unit, a plurality of capacitors, a control unit and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an analog signal. When the sample hold circuit is in a second state, the capacitors eliminate a DC offset voltage of the analog signal sampled by the sample unit, and the hold unit outputs an AC signal of the analog signal sampled by the sample unit. The control unit adjusts a number of the capacitances coupled to a common voltage according to a magnitude of the DC offset voltage, thus to determine the capacitance for eliminating the DC offset voltage.

摘要翻译： 提供了采样保持电路和消除模拟信号偏移电压的方法。 采样保持电路包括采样单元，多个电容器，控制单元和保持单元。 当采样保持电路处于第一状态时，采样单元对模拟信号进行采样。 当采样保持电路处于第二状态时，电容器消除由采样单元采样的模拟信号的DC偏移电压，并且保持单元输出由采样单元采样的模拟信号的AC信号。 控制单元根据DC偏移电压的大小调整与公共电压耦合的电容数，从而确定用于消除DC偏移电压的电容。

公开(公告)号：US20110058692A1

公开(公告)日：2011-03-10

申请号：US12555942

申请日：2009-09-09

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： H03F99/00

CPC分类号： H03F1/305 ,  H03F3/68 ,  H03F2200/321 ,  H03G3/348

摘要： An audio output device is provided and includes a power source, a controller, a signal generating circuit, and a first amplifier. The power source provides a supply voltage signal. The controller receives the supply voltage signal. The controller further compares the supply voltage signal with a threshold voltage signal and generates a control signal according to the comparison result. The signal generating circuit generates a first analog signal. The first amplifier receives the first analog signal and generates a first amplified signal according to the control signal.

摘要翻译： 提供一种音频输出装置，包括电源，控制器，信号发生电路和第一放大器。 电源提供电源电压信号。 控制器接收电源电压信号。 控制器还将电源电压信号与阈值电压信号进行比较，并根据比较结果生成控制信号。 信号发生电路产生第一模拟信号。 第一放大器接收第一模拟信号并根据控制信号产生第一放大信号。

公开(公告)号：US20100085227A1

公开(公告)日：2010-04-08

申请号：US12247186

申请日：2008-10-07

申请人： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

发明人： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC分类号： H03M1/10

CPC分类号： H03M1/1225 ,  H03M1/0695 ,  H03M1/162 ,  H03M1/164 ,  H03M1/40 ,  H03M1/44

摘要： An analog-to-digital converter (ADC) for pipelined ADCs or cyclic ADCs is disclosed. The ADC includes at least one pair of two stages connected in series, and the two stages have different bits of resolution. An amplifier is shared by the pair of two stages such that the two stages operate in an interleaved manner. Accordingly, this stage-resolution scalable opamp-sharing technique is adaptable for pipelined ADC or cyclic ADC, which substantially reduces power consumption and increases operating speed.

摘要翻译： 公开了一种用于流水线ADC或循环ADC的模数转换器（ADC）。 ADC包括串联连接的至少一对两级，两级具有不同的分辨率。 放大器由一对两个级共享，使得两个级以交错方式操作。 因此，这种阶段分辨率可扩展的运算放大器共享技术适用于流水线ADC或循环ADC，这大大降低了功耗并提高了运行速度。

公开(公告)号：US20090278601A1

公开(公告)日：2009-11-12

申请号：US12149650

申请日：2008-05-06

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F2200/405 ,  H03F2203/45048 ,  H03F2203/45101

摘要： A preamplifier includes cascade-connected amplifying circuits, and at least one of the cascade-connected amplifying circuits includes a differential switch pair circuit, a comparator and energy storing elements. The differential switch pair circuit has a pair of differential inputs and a pair of differential outputs. The comparator -outputs a comparison signal by comparing the differential outputs. The energy storing elements are respectively and selectively coupled to one of the differential outputs based on the comparison signal to adjust potential of the differential outputs. A method for calibrating offsets in a preamplifier is also disclosed herein.

摘要翻译： 前置放大器包括级联连接的放大电路，并且串联连接的放大电路中的至少一个包括差分开关对电路，比较器和能量存储元件。 差分开关对电路具有一对差分输入和一对差分输出。 比较器 - 通过比较差分输出输出比较信号。 基于比较信号，能量存储元件分别选择性地耦合到差分输出中的一个，以调整差分输出的电位。 本文还公开了用于校准前置放大器中的偏移的方法。

公开(公告)号：US20090134914A1

公开(公告)日：2009-05-28

申请号：US11945797

申请日：2007-11-27

申请人： Chih-Haur HUANG

发明人： Chih-Haur HUANG

IPC分类号： H03K5/22

CPC分类号： H03K5/24

摘要： A low offset comparator includes a preamplifier and a latch. The preamplifier includes a first output offset storage stage, a cascade of input offset storage stages and a second output offset storage stage. The first output offset storage stage receives an input voltage. The cascade of input offset storage stages is connected to follow the first output offset storage stage. The second output offset storage stage is connected to follow the input offset storage stages. The latch is connected to follow the preamplifier. The low offset comparator is characterized in that the cascade of input offset storage stages, the second output offset storage stage and the first output offset storage stage are configured to sequentially leave an offset cancellation mode, and the input offset storage stages, when leaving the offset cancellation mode, are to open their unity-gain feedback loops before disconnecting their input offset storages from a ground voltage.

摘要翻译： 低偏移比较器包括前置放大器和锁存器。 前置放大器包括第一输出偏移存储级，级联的输入偏移存储级和第二输出偏移存储级。 第一输出偏移存储级接收输入电压。 输入偏移存储级的级联连接到第一输出偏移存储级。 连接第二输出偏移存储级以跟随输入偏移存储级。 锁存器连接以跟随前置放大器。 低偏移比较器的特征在于，输入偏移存储级，第二输出偏移存储级和第一输出偏移存储级的级联被配置为顺序地保留偏移消除模式，并且输入偏移存储级在离开偏移 取消模式是在断开其输入偏移存储器与接地电压之前打开它们的单位增益反馈回路。

公开(公告)号：US20090096498A1

公开(公告)日：2009-04-16

申请号：US11907175

申请日：2007-10-10

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H03L7/0996

摘要： A receiver system is provided. The receiver system includes a control unit for outputting a control signal and a selective signal, a PLL unit for generates PLL clock signals based on an initial clock signal, a phase select unit for selecting one of the PLL clock signals as a base clock signal according to the selective signal, a DLL unit for generating DLL clock signals based on the base clock signal, a sampling clock unit for generating left and right clock signals based on the DLL clock signals and a data latch unit for sampling bit data according to the left, DLL, and right clock signals to obtain left, middle and right data, which are feedback to the control unit for outputting the control signal and the selective signal to adjust the left, DLL and right clock signals or select the base clock signal for next bit data.

摘要翻译： 提供接收机系统。 接收机系统包括用于输出控制信号和选择信号的控制单元，用于基于初始时钟信号产生PLL时钟信号的PLL单元，用于选择PLL时钟信号之一作为基本时钟信号的相位选择单元， 基于所述基本时钟信号生成DLL时钟信号的DLL单元，基于所述DLL时钟信号生成左右时钟信号的采样时钟单元，以及根据左侧的位数据采样的数据锁存单元 ，DLL和右时钟信号，以获得左，中，右数据，其反馈到控制单元以输出控制信号和选择信号以调整左，右和右时钟信号或选择下一个基本时钟信号 位数据。

公开(公告)号：US20090091356A1

公开(公告)日：2009-04-09

申请号：US11905796

申请日：2007-10-04

申请人： Chih-Haur Huang ,  Yuan-Kai Chu

发明人： Chih-Haur Huang ,  Yuan-Kai Chu

IPC分类号： H02M11/00

CPC分类号： H04L25/0278

摘要： A current-mode differential transmitter, receiving a single-end input voltage signal and accordingly generating a differential output current signal, is provided. The transmitter includes a first switch, a second switch and a current mirror. The first switch is coupled in a first current path and controlled by the single-end input voltage signal. The second switch is coupled in a second current path and controlled by an inverted signal of the single-end input voltage signal. The current mirror mirrors a reference current to the first current path when the first switch is turned on, and mirrors the reference current to the second current path when the second switch is turned on. The differential output current signal is derived from the currents on the first and second current paths.

摘要翻译： 提供了接收单端输入电压信号并因此产生差分输出电流信号的电流模式差分发射器。 发射机包括第一开关，第二开关和电流镜。 第一开关耦合在第一电流路径中并由单端输入电压信号控制。 第二开关耦合在第二电流路径中并由单端输入电压信号的反相信号控制。 当第一开关导通时，电流镜反射到第一电流路径的参考电流，并且当第二开关导通时将电流反射到第二电流路径的参考电流。 差分输出电流信号从第一和第二电流路径上的电流导出。

公开(公告)号：US08390501B2

公开(公告)日：2013-03-05

申请号：US13096908

申请日：2011-04-28

申请人： Soon-Jyh Chang ,  Guan-Ying Huang ,  Chun-Cheng Liu ,  Chung-Ming Huang ,  Jin-Fu Lin ,  Chih-Haur Huang

发明人： Soon-Jyh Chang ,  Guan-Ying Huang ,  Chun-Cheng Liu ,  Chung-Ming Huang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC分类号： H03M1/34

CPC分类号： H03M1/462 ,  H03M1/466

摘要： A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window. The SAR controller decodes the outputs of the first and second coarse comparators and the fine comparator to obtain a converted output of the SAR ADC.

摘要翻译： 公开了逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。 第一和第二电容器DAC分别接收第一和第二输入信号。 第一粗略比较器将第一电容器DAC的输出与窗口参考电压进行比较，第二粗略比较器将第二电容器DAC的输出与窗口参考电压进行比较，精细比较器将第一电容器DAC的输出与 第二电容DAC的输出。 SAR控制器接收第一和第二粗略比较器的输出，以确定第一和第二电容器DAC的输出是否在由窗口参考电压确定的预测窗口内。 当第一电容器DAC和第二电容器DAC的输出被确定为在预测窗口内时，SAR控制器绕过至少一个SAR模数转换阶段。 SAR控制器解码第一和第二粗略比较器和精细比较器的输出，以获得SAR ADC的转换输出。

公开(公告)号：US20120281857A1

公开(公告)日：2012-11-08

申请号：US13552368

申请日：2012-07-18

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： H04B15/00 ,  H03F99/00

CPC分类号： H03F1/0261 ,  H03F1/305 ,  H03F3/187 ,  H03F3/45475 ,  H03F2200/03 ,  H03F2203/45138 ,  H03F2203/45528

摘要： An audio amplifier includes a timing control circuit, an amplifying circuit, and a bias control circuit. The timing control circuit generates a first power down signal and a second power down signal, in which the first power down signal is asserted before the second power down signal is asserted. The amplifying circuit receives a bias voltage to amplify an audio signal and is deactivated when the first power down signal is asserted. The bias control circuit provides the bias voltage for the amplifying circuit and is deactivated when the second power down signal is asserted.

摘要翻译： 音频放大器包括定时控制电路，放大电路和偏置控制电路。 定时控制电路产生第一掉电信号和第二掉电信号，其中在断言第二掉电信号之前断言第一掉电信号。 放大电路接收偏置电压以放大音频信号，并且当第一掉电信号被断言时，放大电路被去激活。 偏置控制电路为放大电路提供偏置电压，并且在断言第二次掉电信号时被去激活。