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    Methods of forming wiring layers on integrated circuits including regions of high and low topography
    23.
    发明授权
    Methods of forming wiring layers on integrated circuits including regions of high and low topography 失效
    在包括高低地形地区的集成电路上形成布线层的方法

    公开(公告)号：US6140174A

    公开(公告)日：2000-10-31

    申请号：US338708

    申请日：1999-06-23

    Applicant: Chul-Soon Kwon ,  Ju-Won jang ,  Yong-Bae Choi

    Inventor： Chul-Soon Kwon ,  Ju-Won jang ,  Yong-Bae Choi

    IPC: H01L27/108 ,  H01L21/8242

    CPC classification number: H01L27/10894 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882

    Abstract: Integrated circuits include an integrated circuit substrate and a plurality of active regions and isolation regions in the integrated circuit substrate. A plurality of conductive and insulating layers are included on the integrated circuit substrate that define regions of high and low topography on the integrated circuit substrate. An underlying wiring layer is provided on the low topography region, but not on the high topography region. An overlying wiring layer is provided on the low topography region and on the high topography region. An insulating layer is provided between the underlying wiring layer and the overlying wiring layer. Memory integrated circuit, DRAM integrated circuit, MML integrated circuit and MDL integrated circuit embodiments may be provided.

    Abstract translation: 集成电路包括集成电路基板和集成电路基板中的多个有源区域和隔离区域。 在集成电路基板上包括多个导电绝缘层，其限定集成电路基板上的高和低地形图。 下部布线层设置在低地形区域上，但不在高地形区域上。 在低地形区域和高地形区域上设置覆盖的布线层。 在下层布线层和上覆布线层之间设置绝缘层。 可以提供存储器集成电路，DRAM集成电路，MML集成电路和MDL集成电路实施例。

    Method of manufacturing a non-volatile memory device
    25.
    发明申请
    Method of manufacturing a non-volatile memory device 审中-公开
    制造非易失性存储器件的方法

    公开(公告)号：US20070042539A1

    公开(公告)日：2007-02-22

    申请号：US11504422

    申请日：2006-08-15

    Applicant: Young-Cheon Jeong ,  Chul-Soon Kwon ,  Jae-Min Yu ,  Jae-Hyun Park ,  Ji-Woon Rim ,  In-Gu Yoon

    Inventor： Young-Cheon Jeong ,  Chul-Soon Kwon ,  Jae-Min Yu ,  Jae-Hyun Park ,  Ji-Woon Rim ,  In-Gu Yoon

    IPC: H01L21/8238

    CPC classification number: H01L29/7881 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11543 ,  H01L29/40114 ,  H01L29/42324

    Abstract: In a method of manufacturing a non-volatile memory device, a first gate insulation layer and a conductive layer are formed on a substrate and then the conductive layer is partially oxidized to form an oxide layer pattern. The conductive layer is partially etched using the oxide layer pattern as an etching mask to form a floating gate electrode on the first gate insulation layer and then the silicon layer is formed on the substrate including the floating gate electrode. The silicon layer is oxidized to form a tunnel insulation layer and a second gate insulation layer on a sidewall of the floating gate electrode and on a surface portion of the substrate adjacent to the floating gate electrode and then a control gate electrode is formed on the tunnel insulation layer and the second gate insulation layer.

    Abstract translation: 在制造非易失性存储器件的方法中，在衬底上形成第一栅极绝缘层和导电层，然后导电层被部分氧化以形成氧化物层图案。 使用氧化物层图案作为蚀刻掩模来部分蚀刻导电层，以在第一栅极绝缘层上形成浮置栅电极，然后在包括浮置栅电极的基板上形成硅层。 硅层被氧化以在浮栅电极的侧壁上和基板的与浮置栅电极相邻的表面部分上形成隧道绝缘层和第二栅极绝缘层，然后在隧道上形成控制栅电极 绝缘层和第二栅极绝缘层。

    Method of forming a conductive pattern of a semiconductor device and method of manufacturing a non-volatile semiconductor memory device using the same
    26.
    发明授权
    Method of forming a conductive pattern of a semiconductor device and method of manufacturing a non-volatile semiconductor memory device using the same 有权
    形成半导体器件的导电图案的方法和使用该半导体器件的非易失性半导体存储器件的制造方法

    公开(公告)号：US07081380B2

    公开(公告)日：2006-07-25

    申请号：US10782782

    申请日：2004-02-23

    Applicant: Don-Woo Lee ,  Chul-Soon Kwon ,  Chang-Yup Lee

    Inventor： Don-Woo Lee ,  Chul-Soon Kwon ,  Chang-Yup Lee

    IPC: H01L21/8238

    CPC classification number: H01L29/66825 ,  H01L21/7684

    Abstract: A method of forming a conductive pattern of a semiconductor device includes forming a conductive layer is on a substrate, forming a polishing protection layer on the substrate including over the conductive layer, and forming a step compensation layer on the polishing protection layer to reduce the step presented by the layer that is the polishing protection layer. The conductive layer is the exposed by removing select portions of the step compensation layer and the polishing protection layer. The conductive pattern is ultimately formed on the substrate by etching the exposed conductive layer. By planarization the intermediate structure several times once the step compensation layer is formed, a highly uniform conductive layer is sure to be formed.

    Abstract translation: 形成半导体器件的导电图案的方法包括在基板上形成导电层，在包括在导电层上的衬底上形成抛光保护层，并在抛光保护层上形成台阶补偿层，以减少步骤 由抛光保护层的层呈现。 通过去除步进补偿层和抛光保护层的选择部分来暴露导电层。 通过蚀刻暴露的导电层，最终在衬底上形成导电图案。 通过中间结构的平面化，一旦形成了阶梯补偿层，就可以确保形成高度均匀的导电层。

    Flash memory device having a split gate
    29.
    发明授权
    Flash memory device having a split gate 有权
    具有分闸的闪存器件

    公开(公告)号：US07564092B2

    公开(公告)日：2009-07-21

    申请号：US11503126

    申请日：2006-08-14

    Applicant: Eui-youl Ryu ,  Chul-soon Kwon ,  Jin-woo Kim ,  Yong-hee Kim ,  Dai-geun Kim ,  Joo-chan Kim

    Inventor： Eui-youl Ryu ,  Chul-soon Kwon ,  Jin-woo Kim ,  Yong-hee Kim ,  Dai-geun Kim ,  Joo-chan Kim

    IPC: H01L29/76 ,  H01L29/788

    CPC classification number: H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

    Abstract: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.

    Abstract translation: 具有能够防止有源区域和浮栅电极不对准的分离栅极的闪存器件及其制造方法包括在半导体衬底上依次层叠栅极氧化物层和浮置栅极导电层，形成 在形成有浮栅导电层的半导体衬底的预定区域中形成隔离层，并限定有源区。 然后，通过在活性区域上氧化浮栅导电层的预定部分来形成局部氧化层。 通过使用局部氧化物层图案化浮栅导电层来形成浮栅电极结构。

    Nonvolatile memory device and method of fabricating the same
    30.
    发明授权
    Nonvolatile memory device and method of fabricating the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US07560765B2

    公开(公告)日：2009-07-14

    申请号：US11624464

    申请日：2007-01-18

    Applicant: Jung-ho Moon ,  Chul-soon Kwon ,  Jae-min Yu ,  Jae-hyun Park ,  Young-cheon Jeong ,  In-gu Yoon

    Inventor： Jung-ho Moon ,  Chul-soon Kwon ,  Jae-min Yu ,  Jae-hyun Park ,  Young-cheon Jeong ,  In-gu Yoon

    IPC: H01L29/788

    CPC classification number: H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

    Abstract: A nonvolatile memory device includes a semiconductor substrate; a source region that is formed in the semiconductor substrate; a gate insulating film that is formed so as to partially overlap the source region on the semiconductor substrate; a floating gate that is formed on the gate insulating film so as to have a structure forming a uniform electric field in the portion that overlaps the source region; a control gate that is formed so as to be electrically isolated along one sidewall of the floating gate from an upper part of the floating gate, an inter-gate insulating film that is interposed between the floating gate and the control gate, and a drain region that is formed so as to be adjacent the other side of the control gate.

    Abstract translation: 非易失性存储器件包括半导体衬底; 源区域，其形成在所述半导体衬底中; 形成为与半导体衬底上的源极区域重叠的栅极绝缘膜; 形成在所述栅极绝缘膜上的浮栅，以具有在与所述源极区重叠的部分中形成均匀电场的结构; 形成为从浮置栅极的上部的浮动栅极的一个侧壁电绝缘的控制栅极，插入在浮置栅极和控制栅极之间的栅极间绝缘膜，以及漏极区域 其形成为与控制栅极的另一侧相邻。

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