公开(公告)号：US20130207187A1

公开(公告)日：2013-08-15

申请号：US13372037

申请日：2012-02-13

Applicant: Ker Hsiao HUO ,  Chih-Chang CHENG ,  Ru-Yi SU ,  Jen-Hao YEH ,  Fu-Chih YANG ,  Chun Lin TSAI

Inventor： Ker Hsiao HUO ,  Chih-Chang CHENG ,  Ru-Yi SU ,  Jen-Hao YEH ,  Fu-Chih YANG ,  Chun Lin TSAI

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7394 ,  H01L21/26533 ,  H01L21/76243 ,  H01L21/76283 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66325 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7824 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

Abstract translation: 在本公开中提供了高电压金属氧化物半导体横向扩散器件（HV LDMOS），特别是绝缘栅双极结型晶体管（IGBT）及其制造方法。 该器件包括半导体衬底，形成在衬底上的栅极结构，在栅极结构的任一侧上的衬底中形成的源极和漏极，在衬底中形成的第一掺杂阱和形成在第一衬底中的第二掺杂阱 好。 栅极，源极，第二掺杂阱，第一阱的一部分和漏极结构的一部分被硅衬底中的深沟槽隔离特征和注入的氧层包围。

公开(公告)号：US20130146893A1

公开(公告)日：2013-06-13

申请号：US13760496

申请日：2013-02-06

Applicant: Kong-Beng THEI ,  Jiun-Lei Jerry YU ,  Chun Lin TSAI ,  Hsiao-Chin TUAN ,  Alex KALNITSKY

Inventor： Kong-Beng THEI ,  Jiun-Lei Jerry YU ,  Chun Lin TSAI ,  Hsiao-Chin TUAN ,  Alex KALNITSKY

IPC: H01L27/06

CPC classification number: H01L27/0617 ,  H01L21/26506 ,  H01L21/8258 ,  H01L27/085 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A silicon substrate with a GaN-based device and a Si-based device on the silicon substrate is provided. The silicon substrate includes the GaN-based device on a SiC crystalline region. The SiC crystalline region is formed in the silicon substrate. The silicon substrate also includes the Si-based device on a silicon region, and the silicon region is next to the SiC crystalline region on the silicon substrate.

Abstract translation: 提供了在硅衬底上具有GaN基器件和Si基器件的硅衬底。 硅衬底包括SiC结晶区上的GaN基器件。 在硅衬底中形成SiC晶体区域。 硅衬底还包括在硅区域上的基于Si的器件，并且硅区域位于硅衬底上的SiC晶体区域的旁边。

公开(公告)号：US20120280361A1

公开(公告)日：2012-11-08

申请号：US13100714

申请日：2011-05-04

Applicant: Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

Inventor： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC: H01L29/8605 ,  H01L21/02

CPC classification number: H01L28/20 ,  H01L27/0207 ,  H01L27/0802

Abstract: Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L.

Abstract translation: 提供高压半导体器件。 半导体器件包括位于衬底中的相对掺杂的掺杂阱。 半导体器件包括位于掺杂阱上的电介质结构。 邻近电介质结构的掺杂阱的一部分具有比掺杂阱的剩余部分更高的掺杂浓度。 半导体器件包括位于电介质结构上的细长多晶硅结构。 细长多晶硅结构具有长度L.与电介质结构相邻的掺杂阱的部分电耦合到细长多晶硅结构的段，其远离细长多晶硅结构的中点远离所测量的预定距离 细长多晶硅结构。 预定距离在从大约0 * L到大约0.1 * L的范围内。

公开(公告)号：US20120181629A1

公开(公告)日：2012-07-19

申请号：US13007220

申请日：2011-01-14

Applicant: Ru-Yi Su ,  Fu-Chih Yang ,  Chun-Lin Tsai ,  Ker Hsiao Huo ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

Inventor： Ru-Yi Su ,  Fu-Chih Yang ,  Chun-Lin Tsai ,  Ker Hsiao Huo ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC: H01L29/78

CPC classification number: H01L29/7835 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7816 ,  H01L29/861

Abstract: A device includes a first and a second heavily doped region in a semiconductor substrate. An insulation region has at least a portion in the semiconductor substrate, wherein the insulation region is adjacent to the first and the second heavily doped regions. A gate dielectric is formed over the semiconductor substrate and having a portion over a portion of the insulation region. A gate is formed over the gate dielectric. A floating conductor is over and vertically overlapping the insulation region. A metal line includes a portion over and vertically overlapping the floating conductor, wherein the metal line is coupled to, and carries a voltage of, the second heavily doped region.

Abstract translation: 一种器件包括半导体衬底中的第一和第二重掺杂区域。 绝缘区域在半导体衬底中具有至少一部分，其中绝缘区域与第一和第二重掺杂区域相邻。 栅极电介质形成在半导体衬底之上并且具有在绝缘区域的一部分上的部分。 栅极形成在栅极电介质上。 浮动导体在绝缘区域上方和上方重叠。 金属线包括在浮动导体上方并垂直重叠的部分，其中金属线与第二重掺杂区耦合并承载第二重掺杂区的电压。

公开(公告)号：US20120139041A1

公开(公告)日：2012-06-07

申请号：US12959538

申请日：2010-12-03

Applicant: Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker Hsiao Huo ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

Inventor： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker Hsiao Huo ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7816 ,  H01L21/76202 ,  H01L27/0629 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/861

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region.

Abstract translation: 本发明提供一种半导体器件。 半导体器件包括：漂移区，其具有形成在衬底中的第一掺杂极性; 掺杂的延伸区域形成在所述漂移区域中并具有与所述第一掺杂极性相反的第二掺杂极性，所述掺杂延伸区域包括横向延伸的部件; 在所述漂移区上形成的电介质结构，所述电介质结构通过所述漂移区的一部分与所述掺杂延伸区分离; 形成在电介质结构的一部分上的栅结构和掺杂延伸区的一部分; 以及具有第二掺杂极性的掺杂隔离区，所述掺杂隔离区至少部分地围绕所述漂移区和所述掺杂延伸区。

公开(公告)号：US20120132995A1

公开(公告)日：2012-05-31

申请号：US12956025

申请日：2010-11-30

Applicant: Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai

Inventor： Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai

IPC: H01L27/06 ,  H01L21/02

CPC classification number: H01L27/0288 ,  H01L23/5256 ,  H01L27/0255 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided.

Abstract translation: 本公开提供了一种半导体器件，其包括晶体管，其包括衬底，源极，漏极和栅极以及堆叠在晶体管上的熔丝。 保险丝包括耦合到晶体管的漏极的阳极触点，阴极触点和分别经由第一肖特基二极管和第二肖特基二极管耦合到阴极触点和阳极触点的电阻器。 还提供了一种制造这种半导体器件的方法。

公开(公告)号：US20120119265A1

公开(公告)日：2012-05-17

申请号：US12944959

申请日：2010-11-12

Applicant: Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

Inventor： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC: H01L29/78 ,  H01L21/22 ,  H01L21/336

CPC classification number: H01L29/7816 ,  H01L21/2253 ,  H01L21/26513 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/105 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7835

Abstract: The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.

Abstract translation: 本公开提供了一种用于制造高压半导体器件的方法。 该方法包括在衬底中指定第一，第二和第三区域。 第一和第二区域分别是将形成半导体器件的源极和漏极的区域。 第三区域分隔第一和第二区域。 该方法还包括至少部分地在第三区域上形成开槽的注入掩模层。 该方法还包括将掺杂剂注入到第一，第二和第三区域中。 开槽植入物掩模层在植入期间保护其下方的第三区域的部分。 该方法还包括以使得掺杂剂在第三区域中扩散的方式退火衬底。

公开(公告)号：US08158475B2

公开(公告)日：2012-04-17

申请号：US12879777

申请日：2010-09-10

Applicant: Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

Inventor： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

IPC: H01L21/336

CPC classification number: H01L29/4983 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.

Abstract translation: 半导体结构包括半导体衬底; 覆盖半导体衬底的第一导电类型的第一高电压阱（HVW）区域; 第二导电类型的第二阱区域，与覆盖半导体衬底并横向邻接第一阱区的第一导电类型相反; 栅极电介质，其从所述第一阱区域上延伸到所述第二阱区域上方; 第二阱区中的漏极区; 栅极电介质的与漏极区相反的一侧的源极区; 和栅电极上的栅电极。 栅电极包括直接在第二阱区上的第一部分和直接在第一阱区上的第二部分。 第一部分具有低于第二部分的第二杂质浓度的第一杂质浓度。

公开(公告)号：US20120061681A1

公开(公告)日：2012-03-15

申请号：US12881505

申请日：2010-09-14

Applicant: Kong-Beng THEI ,  Jiun-Lei Jerry YU ,  Chun Lin TSAI ,  Hsiao-Chin TUAN ,  Alex KALNITSKY

Inventor： Kong-Beng THEI ,  Jiun-Lei Jerry YU ,  Chun Lin TSAI ,  Hsiao-Chin TUAN ,  Alex KALNITSKY

IPC: H01L29/12 ,  H01L21/265

CPC classification number: H01L27/0617 ,  H01L21/26506 ,  H01L21/8258 ,  H01L27/085 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The mechanisms of forming SiC crystalline regions on Si substrate described above enable formation and integration of GaN-based devices and Si-based devices on a same substrate. The SiC crystalline regions are formed by implanting carbon into regions of Si substrate and then annealing the substrate. An implant-stop layer is used to cover the Si device regions during formation of the SiC crystalline regions.

Abstract translation: 在上述Si衬底上形成SiC结晶区的机理能够在同一衬底上形成GaN和GaN基器件的集成。 通过将碳注入到Si衬底的区域中，然后使衬底退火来形成SiC晶体区域。 在形成SiC晶体区域期间，使用注入停止层来覆盖Si器件区域。

公开(公告)号：US20110133276A1

公开(公告)日：2011-06-09

申请号：US12888113

申请日：2010-09-22

Applicant: Kong-Beng Thei ,  Jiun-Lei Jerry Yu ,  Chien-Chih Chou ,  Chun-Lin Tsai

Inventor： Kong-Beng Thei ,  Jiun-Lei Jerry Yu ,  Chien-Chih Chou ,  Chun-Lin Tsai

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/823462 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7835

Abstract: An integrated circuit structure includes a semiconductor substrate and a high-voltage metal-oxide-semiconductor (HVMOS) device, which includes a first high-voltage well (HVW) region of a first conductivity type in the semiconductor substrate; a drain region of a second conductivity type opposite the first conductivity type in the semiconductor substrate and spaced apart from the first HVW region; a gate dielectric with at least a portion directly over the first HVW region; and a gate electrode over the gate dielectric. The gate dielectric includes a bottom gate oxide region; and a silicon nitride region over the bottom gate oxide region.

Abstract translation: 集成电路结构包括半导体衬底和高电压金属氧化物半导体（HVMOS）器件，其包括在半导体衬底中的第一导电类型的第一高电压阱（HVW）区域; 在所述半导体衬底中与所述第一HVW区间隔开的第二导电类型的与所述第一导电类型相反的漏极区; 栅极电介质，其具有直接在所述第一HVW区域上的至少一部分; 以及在栅极电介质上的栅电极。 栅极电介质包括底部栅极氧化物区域; 以及在底部栅极氧化物区域上方的氮化硅区域。