公开(公告)号：US20070249165A1

公开(公告)日：2007-10-25

申请号：US11399084

申请日：2006-04-05

Applicant: Chun-Jen Huang ,  Cheng-Ming Weng ,  Meng-Jun Wang

Inventor： Chun-Jen Huang ,  Cheng-Ming Weng ,  Meng-Jun Wang

IPC: H01L21/4763

CPC classification number: H01L21/76811

Abstract: A dual damascene process is provided. A substrate having a conductive area is provided. An etching stop layer, a dielectric layer and a patterned hard mask layer are sequentially formed on the substrate. A first opening is formed in the dielectric layer exposed by the patterned hard mask layer. A first material layer having a high etching selectivity with respect to the dielectric layer is deposited to fill the first opening. A portion of the dielectric layer and the filling material layer are removed to form a trench and a second opening. The filling material layer exposed by the second opening is removed to expose part of the etching stop layer. A portion of the etching stop layer is removed to form a third opening. A conductive layer is formed in the trench and the third opening.

Abstract translation: 提供了双镶嵌工艺。 提供具有导电区域的基板。 蚀刻停止层，电介质层和图案化的硬掩模层依次形成在基板上。 在由图案化的硬掩模层暴露的电介质层中形成第一开口。 沉积相对于电介质层具有高蚀刻选择性的第一材料层以填充第一开口。 去除介电层和填充材料层的一部分以形成沟槽和第二开口。 去除由第二开口暴露的填充材料层以暴露部分蚀刻停止层。 去除蚀刻停止层的一部分以形成第三开口。 在沟槽和第三开口中形成导电层。

公开(公告)号：US20070155157A1

公开(公告)日：2007-07-05

申请号：US11306590

申请日：2006-01-04

Applicant: Pei-Yu Chou ,  Chun-Jen Huang

Inventor： Pei-Yu Chou ,  Chun-Jen Huang

IPC: H01L21/4763

CPC classification number: H01L21/76844 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76829

Abstract: A process and structure for a metal interconnect comprises providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.

公开(公告)号：US08269548B2

公开(公告)日：2012-09-18

申请号：US13081472

申请日：2011-04-06

Applicant: Chun-Jen Huang

Inventor： Chun-Jen Huang

IPC: H01L35/00

CPC classification number: G05F3/30

Abstract: General speaking, a resistor of high resistivity has a negative-temperature-coefficient and a resistor of low resistivity has a positive-temperature-coefficient. Utilizing this characteristic, an appropriate proportion between the above resistors can be found to make a combined resistor with an approximate zero-temperature-coefficient. The combined resistor can be used to design a circuit for generating voltage and current with approximate zero-temperature-coefficients.

Abstract translation: 一般来说，高电阻率的电阻器具有负温度系数，低电阻率的电阻器具有正温度系数。 利用该特性，可以发现上述电阻器之间的适当比例使得具有近似零温度系数的组合电阻器。 组合电阻器可用于设计用于产生具有近似零温度系数的电压和电流的电路。

公开(公告)号：US07524742B2

公开(公告)日：2009-04-28

申请号：US11748472

申请日：2007-05-14

Applicant: Pei-Yu Chou ,  Chun-Jen Huang

Inventor： Pei-Yu Chou ,  Chun-Jen Huang

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L21/76844 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76829

Abstract: A process and structure for a metal interconnect includes providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.

Abstract translation: 金属互连的工艺和结构包括：使用第一图案化硬掩模提供具有第一电导体的基板，形成第一介电层和第一图案化硬掩模，以形成第一开口和第二导电体，形成第二导体 电介质层和第二图案化硬掩模，使用第二图案化硬掩模作为蚀刻掩模，并使用第一图案化硬掩模作为蚀刻停止层以形成第二开口和第三导电体。

公开(公告)号：US20070090360A1

公开(公告)日：2007-04-26

申请号：US11415522

申请日：2006-05-02

Applicant: Sheng-Huei Dai ,  Ya-Chin King ,  Chun-Jen Huang ,  L.C. Kao

Inventor： Sheng-Huei Dai ,  Ya-Chin King ,  Chun-Jen Huang ,  L.C. Kao

IPC: H01L29/04 ,  H01L21/00 ,  H01L29/15 ,  H01L29/10 ,  H01L31/00 ,  H01L31/036

CPC classification number: H01L29/8611 ,  H01L29/66136

Abstract: Blanket implant diode which can be used for transient voltage suppression having a P+ substrate implanted with an N-type dopant blanket implant near a top surface of the substrate, creating a P− region. An oxide mask is layered adjacent to and above the P− region. The oxide mask is partially etched away from a portion of the P− region, creating an etched region. An N-type main function implant is implanted into the etched region, creating an N+ region above the P+ substrate and adjacent the P− region. And, a metal is layered above the oxide mask in the etched region to form an electrode. Terminations may be attached electrically to both sides of the P-N junction. Methods of making and using the present invention and methods for transient voltage suppression are also provided.

Abstract translation: 可以用于瞬态电压抑制的毯式注入二极管，其具有在衬底的顶表面附近注入N型掺杂剂覆盖层注入的P +衬底，形成P-区。 在P区附近层叠氧化物掩模。 氧化物掩模被部分地蚀刻离开P-区域的一部分，产生蚀刻区域。 将N型主要功能植入物注入到蚀刻区域中，在P +衬底上方形成N +区域并邻近P-区域。 并且，在蚀刻区域中的氧化物掩模上方形成金属以形成电极。 端子可以电连接到P-N结的两侧。 还提供了制造和使用本发明的方法和用于瞬态电压抑制的方法。

公开(公告)号：US20060252256A1

公开(公告)日：2006-11-09

申请号：US10908374

申请日：2005-05-09

Applicant: Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

Inventor： Cheng-Ming Weng ,  Miao-Chun Lin ,  Chun-Jen Huang

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/311 ,  H01L21/302

CPC classification number: H01L21/31144 ,  H01L21/02063 ,  H01L21/76811 ,  H01L21/76814 ,  Y10S438/906 ,  Y10S438/963

Abstract: A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped off. A through hole is plasma etched into the low-k dielectric film by using the metal pattern as a hard mask. The plasma etching causes residues to deposit within the through hole. A first wet treatment is then performed to soften the residues. A plasma dry treatment is carried out to crack the residues. A second wet treatment is performed to completely remove the residues.

Abstract translation: 低k绝缘膜沉积在晶片上。 然后在低k电介质膜上沉积金属层。 在金属层上形成抗蚀剂图案。 然后将抗蚀剂图案转移到下面的金属层以形成金属图案。 剥离抗蚀剂图案。 通过使用金属图案作为硬掩模将通孔等离子体蚀刻到低k电介质膜中。 等离子体蚀刻导致残留物沉积在通孔内。 然后进行第一次湿处理以软化残留物。 进行等离子体干燥处理以破坏残留物。 进行第二次湿处理以完全去除残留物。

公开(公告)号：US09214859B2

公开(公告)日：2015-12-15

申请号：US13460112

申请日：2012-04-30

Applicant: Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

Inventor： Yung Feng Lin ,  Chun-Jen Huang ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Caiyun Wu ,  Qifang Wang

IPC: H02M3/07

CPC classification number: H02M3/07

Abstract: In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.

Abstract translation: 在一个方面，第一电荷泵具有串联布置的电荷泵级。 相邻级之间的阶段节点由第二电荷泵泵送。 在另一方面，电荷泵级的定时由命令时钟信号控制。 命令时钟信号和命令数据在与电荷泵的集成电路和外部电路之间传送。

公开(公告)号：US07692960B2

公开(公告)日：2010-04-06

申请号：US11641992

申请日：2006-12-20

Applicant: Chang-Ting Chen ,  Chun-Jen Huang

Inventor： Chang-Ting Chen ,  Chun-Jen Huang

IPC: G11C7/00

CPC classification number: G11C16/0491 ,  G11C16/0475 ,  G11C16/3409

Abstract: A method for improving an over erasing effect of a charge-trapping memory cell. The charge-trapping memory cell has a transistor, which has a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. First, the method erases the charge-trapping memory cell. Then, after the charge-trapping memory cell is completely erased, the first bit line is electrically connected to the second bit line to make a voltage level of the first bit line equal a voltage level of the second bit line such that the voltage level of the first terminal of the transistor equals the voltage level of the second terminal of the transistor.

Abstract translation: 一种用于改善电荷俘获存储单元的擦除效果的方法。 电荷捕获存储单元具有晶体管，其具有耦合到第一位线的第一端子和耦合到第二位线的第二端子。 首先，该方法擦除电荷捕获存储单元。 然后，在电荷捕获存储单元被完全擦除之后，第一位线电连接到第二位线，以使第一位线的电压电平等于第二位线的电压电平，使得第 晶体管的第一端子等于晶体管的第二端子的电压电平。

公开(公告)号：US07474565B2

公开(公告)日：2009-01-06

申请号：US11636920

申请日：2006-12-11

Applicant: Chun-Jen Huang ,  Chia-Jung Chen ,  Hsin-Yi Ho

Inventor： Chun-Jen Huang ,  Chia-Jung Chen ,  Hsin-Yi Ho

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C2211/5621

Abstract: An embodiment of the present invention involves a method of programming a memory cell. The memory cell is in a first state having a maximum initial threshold voltage. The memory cell is to be programmed to one of a plurality of states having a higher target threshold voltage relative to the maximum initial threshold voltage. There is a cue voltage between the maximum initial threshold voltage and the target threshold voltage. The memory cell has a drain region. The method includes applying a drain voltage to the cell by a programming pulse having a first width, determining whether the cell has reached the cue threshold voltage, and if the cell has reached the cue threshold voltage, changing the programming pulse width from the first pulse width to a second pulse width. The second pulse width is smaller than the first pulse width.

Abstract translation: 本发明的一个实施例涉及一种编程存储器单元的方法。 存储单元处于具有最大初始阈值电压的第一状态。 存储器单元将被编程为具有相对于最大初始阈值电压的较高目标阈值电压的多个状态之一。 在最大初始阈值电压和目标阈值电压之间存在一个提示电压。 存储单元具有漏极区域。 该方法包括通过具有第一宽度的编程脉冲向单元施加漏极电压，确定单元是否已经达到提示阈值电压，以及如果单元已经达到提示阈值电压，则从第一脉冲改变编程脉冲宽度 宽度到第二个脉冲宽度。 第二脉冲宽度小于第一脉冲宽度。

公开(公告)号：US20080153243A1

公开(公告)日：2008-06-26

申请号：US12034357

申请日：2008-02-20

Applicant: SHENG-HUEI DAI ,  YA-CHIN KING ,  CHUN-JEN HUANG ,  L.C. KAO

Inventor： SHENG-HUEI DAI ,  YA-CHIN KING ,  CHUN-JEN HUANG ,  L.C. KAO

IPC: H01L21/20

CPC classification number: H01L29/8611 ,  H01L29/66136

Abstract: Blanket implant diode which can be used for transient voltage suppression having a P+ substrate implanted with an N-type dopant blanket implant near a top surface of the substrate, creating a P− region. An oxide mask is layered adjacent to and above the P− region. The oxide mask is partially etched away from a portion of the P− region, creating an etched region. An N-type main function implant is implanted into the etched region, creating an N+ region above the P+ substrate and adjacent the P− region. And, a metal is layered above the oxide mask in the etched region to form an electrode. Terminations may be attached electrically to both sides of the P-N junction. Methods of making and using the present invention and methods for transient voltage suppression are also provided.

Abstract translation: 可以用于瞬态电压抑制的毯式注入二极管，其具有在衬底的顶表面附近注入N型掺杂剂覆盖层注入的P +衬底，形成P-区。 在P区附近层叠氧化物掩模。 氧化物掩模被部分地蚀刻离开P-区域的一部分，产生蚀刻区域。 将N型主要功能植入物注入到蚀刻区域中，在P +衬底上方形成N +区域并邻近P-区域。 并且，在蚀刻区域中的氧化物掩模上方形成金属以形成电极。 端子可以电连接到P-N结的两侧。 还提供了制造和使用本发明的方法和用于瞬态电压抑制的方法。