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    Dual trench isolation for a phase-change memory cell and method of making same
    22.
    发明授权
    Dual trench isolation for a phase-change memory cell and method of making same 有权
    用于相变存储器单元的双沟槽隔离及其制造方法

    公开(公告)号：US06437383B1

    公开(公告)日：2002-08-20

    申请号：US09745322

    申请日：2000-12-21

    Applicant: Daniel Xu

    Inventor： Daniel Xu

    IPC: H01L2972

    CPC classification number: H01L21/76229 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

    Abstract: The invention relates to a phase-change memory device. The device includes a double-trench isolation structure around the diode stack that communicates to the lower electrode. The present invention also relates to a method of making a phase-change memory device. The method includes forming two orthogonal and intersecting isolation trenches around a memory cell structure diode stack.

    Abstract translation: 本发明涉及一种相变存储器件。 该器件包括二极管堆叠周围的双沟槽隔离结构，其与下部电极连通。 本发明还涉及一种制造相变存储器件的方法。 该方法包括在存储单元结构二极管堆叠周围形成两个正交和相交的隔离沟槽。

    Reducing shunts in memories with phase-change material
    24.
    发明授权
    Reducing shunts in memories with phase-change material 有权
    用相变材料减少记忆中的分流

    公开(公告)号：US07161225B2

    公开(公告)日：2007-01-09

    申请号：US11038336

    申请日：2005-01-19

    Applicant: Daniel Xu ,  Chien Chiang

    Inventor： Daniel Xu ,  Chien Chiang

    IPC: H01L29/40 ,  H01L21/00

    CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1683

    Abstract: A memory cell may include a phase-change material. Adhesion between the phase-change material and a dielectric or other substrate may be enhanced by using an adhesion enhancing interfacial layer. Conduction past the phase-change material through the interfacial layer may be reduced by providing a discontinuity or other feature that reduces or prevents conduction along said interfacial layer.

    Abstract translation: 存储单元可以包括相变材料。 可以通过使用粘合增强界面层来增强相变材料与电介质或其它基底之间的粘附。 可以通过提供减少或阻止沿着所述界面层传导的不连续性或其它特征来减少穿过相变材料通过界面层的传导。

    Carbon-containing interfacial layer for phase-change memory
    25.
    发明授权
    Carbon-containing interfacial layer for phase-change memory 有权
    含碳界面层用于相变记忆

    公开(公告)号：US06566700B2

    公开(公告)日：2003-05-20

    申请号：US09975272

    申请日：2001-10-11

    Applicant: Daniel Xu

    Inventor： Daniel Xu

    IPC: H01L27108

    CPC classification number: G11C13/0004 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    Abstract: A phase-change memory cell may be formed with a carbon-containing interfacial layer that heats a phase-change material. By forming the phase-change material in contact, in one embodiment, with the carbon containing interfacial layer, the amount of heat that may be applied to the phase-change material, at a given current and temperature, may be increased. In some embodiments, the performance of the interfacial layer at high temperatures may be improved by using a wide band gap semiconductor material such as silicon carbide.

    Abstract translation: 相变存储器单元可以形成有加热相变材料的含碳界面层。 通过在一个实施方案中通过形成相变材料与含碳界面层，可以增加在给定电流和温度下施加到相变材料的热量。 在一些实施方案中，可以通过使用宽带隙半导体材料如碳化硅来改善界面层在高温下的性能。

    Array architecture for embedded flash memory devices
    26.
    发明授权
    Array architecture for embedded flash memory devices 有权
    嵌入式闪存设备的阵列架构

    公开(公告)号：US08536637B2

    公开(公告)日：2013-09-17

    申请号：US12959279

    申请日：2010-12-02

    Applicant: Daniel Xu ,  Roger Lee

    Inventor： Daniel Xu ,  Roger Lee

    IPC: H01L29/788

    CPC classification number: H01L27/11521 ,  H01L27/11524 ,  H01L29/66575 ,  H01L29/78

    Abstract: A method for manufacturing Flash memory devices includes forming a well region in a substrate, depositing a gate dielectric layer overlying the well region, and depositing a first polysilicon layer overlying the gate dielectric layer. The method also includes depositing a dielectric layer overlying the first polysilicon layer and depositing a second polysilicon layer overlying the dielectric layer to form a stack layer. The method simultaneously patterns the stack layer to form a first flash memory cell, which includes a first portion of the second polysilicon layer overlying a first portion of the dielectric layer overlying a first portion of first polysilicon layer and to form a select device, which includes a second portion of second polysilicon layer overlying a second portion of dielectric layer overlying a second portion of first polysilicon layer. The method further includes forming source/drain regions using ion implant. The select device is activated by applying voltage to the second portion of first polysilicon layer.

    Abstract translation: 一种用于制造闪存器件的方法包括在衬底中形成阱区，沉积覆盖阱区的栅极电介质层，以及沉积覆盖栅极电介质层的第一多晶硅层。 该方法还包括沉积覆盖在第一多晶硅层上的介电层，并沉积覆盖介电层的第二多晶硅层以形成堆叠层。 该方法同时对堆叠层进行图案以形成第一闪存单元，其包括覆盖在第一多晶硅层的第一部分上的介电层的第一部分上的第二多晶硅层的第一部分并且形成选择器件，其包括 覆盖在第一多晶硅层的第二部分上的介电层的第二部分上的第二多晶硅层的第二部分。 该方法还包括使用离子注入形成源极/漏极区域。 通过向第一多晶硅层的第二部分施加电压来激活选择装置。

    Reducing leakage currents in memories with phase-change material
    27.
    发明授权
    Reducing leakage currents in memories with phase-change material 有权
    通过相变材料降低存储器中的漏电流

    公开(公告)号：US07906391B2

    公开(公告)日：2011-03-15

    申请号：US11272308

    申请日：2005-11-10

    Applicant: Daniel Xu ,  Tyler A. Lowery

    Inventor： Daniel Xu ,  Tyler A. Lowery

    IPC: H01L21/00

    CPC classification number: H01L45/06 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/1233 ,  H01L45/144 ,  Y10S257/91

    Abstract: A memory cell including a phase-change material may have reduced leakage current. The cell may receive signals through a buried wordline in one embodiment. The buried wordline may include a sandwich of a more lightly doped N type region over a more heavily doped N type region over a less heavily doped N type region. As a result of the configuration of the N type regions forming the buried wordline, the leakage current of the buried wordline to the substrate under reverse bias conditions may be significantly reduced.

    Abstract translation: 包括相变材料的存储单元可能具有减小的漏电流。 在一个实施例中，小区可以通过掩埋字线接收信号。 掩埋字线可以包括在较重掺杂的N型区域上的更重掺杂的N型区域上的更轻掺杂的N型区域的夹层。 作为形成掩埋字线的N型区域的结构的结果，可以显着地减少掩埋字线在反向偏压条件下对衬底的漏电流。

    Micromachined, piezoelectric vibration-induced energy harvesting device and its fabrication
    28.
    发明授权
    Micromachined, piezoelectric vibration-induced energy harvesting device and its fabrication 有权
    微加工，压电振动诱发能量收集装置及其制造

    公开(公告)号：US07687977B2

    公开(公告)日：2010-03-30

    申请号：US11402017

    申请日：2006-04-10

    Applicant: Zheng Yi-Daniel Xu

    Inventor： Zheng Yi-Daniel Xu

    IPC: H01L41/08

    CPC classification number: H01L41/1136 ,  H01L41/22

    Abstract: A micro-sized power source. A piezoelectric power generator, capable of harvesting energy from environmental vibration with lower level frequency, including a dielectric frame loosely containing a piezoelectric panel. The piezoelectric panel includes an electrode and a piezoelectric layer formed over an electrode and dielectric layer and an end mass formed on the piezoelectric layer. The end mass provides weight to cause the piezoelectric panel to move (vibrate) within the frame and causes the generation of electrical power.

    Abstract translation: 微型电源。 一种压电发电机，能够从具有较低电平频率的环境振动中收集能量，包括松散地包含压电面板的电介质框架。 压电面板包括形成在电极和电介质层上的电极和压电层，以及形成在压电层上的端块。 端部质量提供了重量，以使压电面板在框架内移动（振动）并引起电力的产生。

    Power saving system and method for devices based on universal serial bus
    29.
    发明申请
    Power saving system and method for devices based on universal serial bus 审中-公开
    基于通用串行总线的设备省电系统及方法

    公开(公告)号：US20070192643A1

    公开(公告)日：2007-08-16

    申请号：US11490839

    申请日：2006-07-21

    Applicant: Shi Henry Li ,  Daniel Xu

    Inventor： Shi Henry Li ,  Daniel Xu

    IPC: G06F1/26

    CPC classification number: G06F1/3203 ,  G06F1/3253 ,  Y02D10/151

    Abstract: A system and method for adjusting power consumption of a USB-based device. The system includes a power supply configured to generate a first supply voltage, a controller configured to receive the first supply voltage and generate a control signal, and a USB component configured to receive the control signal and in response operate in a first USB mode or a second USB mode. The controller is further configured to process information associated with the first supply voltage and a predetermined threshold voltage. If the first supply voltage is higher than the predetermined threshold voltage, the control signal represents a first logic state. If the first supply voltage is lower than the predetermined threshold voltage, the control signal represents a second logic state.

    Abstract translation: 一种用于调整基于USB设备的功耗的系统和方法。 该系统包括被配置为产生第一电源电压的电源，被配置为接收第一电源电压并产生控制信号的控制器，以及被配置为接收控制信号并响应于第一USB模式或 第二个USB模式。 控制器还被配置为处理与第一电源电压和预定阈值电压相关联的信息。 如果第一电源电压高于预定阈值电压，则控制信号表示第一逻辑状态。 如果第一电源电压低于预定阈值电压，则控制信号表示第二逻辑状态。

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