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    Wafer-to-wafer alignments
    23.
    发明授权
    Wafer-to-wafer alignments 失效
    晶圆对晶圆对准

    公开(公告)号：US08004289B2

    公开(公告)日：2011-08-23

    申请号：US12198221

    申请日：2008-08-26

    Applicant: Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

    Inventor： Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

    IPC: G01R27/26 ,  G01R31/308

    CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.

    Abstract translation: 用于对准晶片的结构及其操作方法。 该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。 第一和第二半导体晶片经由公共表面彼此直接物理接触。 如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则 包括第一和第二电容耦合结构的第一电容器的电容的至少10-18F的结果。 第一个方向基本上平行于共同的表面。

    THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER
    24.
    发明申请
    THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER 审中-公开
    通过包括插入式灌装机在内的基板

    公开(公告)号：US20110129996A1

    公开(公告)日：2011-06-02

    申请号：US13025678

    申请日：2011-02-11

    Applicant: Peter James Lindgren ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper ,  Kenneth Jay Stein

    Inventor： Peter James Lindgren ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper ,  Kenneth Jay Stein

    IPC: H01L21/28

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.

    Abstract translation: 贯通基板通孔包括在通孔基板孔周边的环形导体层和被环形导体层围绕的塞子层。 一种用于制造贯通衬底通孔的方法，包括在衬底内形成盲孔，并在盲孔内依次形成并随后在盲孔内进行平面化，该保形导体层不填充填充孔的孔和塞层。 然后可以将衬底的背面平坦化以至少露出平坦化的共形导体层。

    Low resistance and inductance backside through vias and methods of fabricating same
    25.
    发明授权
    Low resistance and inductance backside through vias and methods of fabricating same 有权
    低电阻和电感背面穿过通孔及其制造方法

    公开(公告)号：US07851923B2

    公开(公告)日：2010-12-14

    申请号：US12410728

    申请日：2009-03-25

    Applicant: Mete Erturk ,  Robert A. Groves ,  Jeffrey Bowman Johnson ,  Alvin Jose Joseph ,  Qizhi Liu ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper

    Inventor： Mete Erturk ,  Robert A. Groves ,  Jeffrey Bowman Johnson ,  Alvin Jose Joseph ,  Qizhi Liu ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper

    IPC: H01L23/48

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.

    Abstract translation: 背面接触结构及其制造方法。 该方法包括：在衬底中形成电介质隔离，所述衬底具有前侧和相对的背面; 在所述基板的前侧形成第一电介质层; 在所述第一电介质层中形成沟槽，所述沟槽在所述电介质隔离的周边内并且在所述介电隔离的周边内对准并且延伸到所述电介质隔 将形成在第一电介质层中的沟槽通过电介质隔离延伸到衬底中至小于衬底厚度的深度; 填充沟槽并将沟槽的顶表面与第一介电层的顶表面共平面化以形成导电通孔; 并从衬底的背面稀释衬底以露出通孔。

    THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER
    26.
    发明申请
    THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER 有权
    通过包括插入式灌装机在内的基板

    公开(公告)号：US20090206488A1

    公开(公告)日：2009-08-20

    申请号：US12032642

    申请日：2008-02-16

    Applicant: Peter James Lindgren ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper ,  Kenneth Jay Stein

    Inventor： Peter James Lindgren ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper ,  Kenneth Jay Stein

    IPC: H01L21/768 ,  H01L23/538

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.

    Abstract translation: 贯通基板通孔包括在通孔基板孔周边的环形导体层和被环形导体层围绕的塞子层。 一种用于制造贯通衬底通孔的方法，包括在衬底内形成盲孔，并在盲孔内依次形成并随后在盲孔内进行平面化，该保形导体层不填充填充孔的孔和塞层。 然后可以将衬底的背面平坦化以至少露出平坦化的共形导体层。

    Low resistance and inductance backside through vias and methods of fabricating same
    27.
    发明授权
    Low resistance and inductance backside through vias and methods of fabricating same 有权
    低电阻和电感背面穿过通孔及其制造方法

    公开(公告)号：US07563714B2

    公开(公告)日：2009-07-21

    申请号：US11275542

    申请日：2006-01-13

    Applicant: Mete Erturk ,  Robert A. Groves ,  Jeffrey Bowman Johnson ,  Alvin Jose Joseph ,  Qizhi Liu ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper

    Inventor： Mete Erturk ,  Robert A. Groves ,  Jeffrey Bowman Johnson ,  Alvin Jose Joseph ,  Qizhi Liu ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper

    IPC: H01L21/44

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter Of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.

    Abstract translation: 背面接触结构及其制造方法。 该方法包括：在衬底中形成电介质隔离，所述衬底具有前侧和相对的背面; 在所述基板的前侧形成第一电介质层; 在所述第一电介质层中形成沟槽，所述沟槽在所述电介质隔离的周边内并且在所述介质隔离的周边内对准并且延伸到所述电介质隔离; 将形成在第一电介质层中的沟槽通过电介质隔离延伸到衬底中至小于衬底厚度的深度; 填充沟槽并将沟槽的顶表面与第一介电层的顶表面共平面化以形成导电通孔; 并从衬底的背面稀释衬底以露出通孔。

    Stacked chip security
    28.
    发明授权
    Stacked chip security 有权
    堆叠芯片安全

    公开(公告)号：US07557597B2

    公开(公告)日：2009-07-07

    申请号：US11145423

    申请日：2005-06-03

    Applicant: Brent Alan Anderson ,  Edmund Juris Sprogis

    Inventor： Brent Alan Anderson ,  Edmund Juris Sprogis

    IPC: G01R31/02

    CPC classification number: H01L23/585 ,  H01L23/576 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/48227 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: The present invention is directed to an integrated circuit module device. The device includes a first semiconductor chip having a first circuit layer and at least one first interconnection element disposed on a first chip surface. The at least one first interconnection element is electrically coupled to the first circuit layer. A second semiconductor chip includes a second circuit layer and at least one second interconnection element disposed on a second chip surface. The at least one second interconnection element is electrically coupled to the second circuit layer. The at least one first interconnection element is connected to the at least one second interconnection element to establish electrical continuity between the first circuit layer and the second circuit layer. The first surface is adjoined to the second surface. At least one ring delay circuit includes a first ring delay path partially disposed on the first circuit layer and a second ring delay path partially disposed on the second circuit layer. The first ring delay path and the second ring delay path form a signal path having a predetermined measurement signature. The ring delay circuit compares the predetermined measurement signature to a test measurement signature.

    Abstract translation: 本发明涉及一种集成电路模块装置。 该器件包括具有第一电路层的第一半导体芯片和设置在第一芯片表面上的至少一个第一互连元件。 所述至少一个第一互连元件电耦合到所述第一电路层。 第二半导体芯片包括第二电路层和设置在第二芯片表面上的至少一个第二互连元件。 所述至少一个第二互连元件电耦合到第二电路层。 所述至少一个第一互连元件连接到所述至少一个第二互连元件，以在所述第一电路层和所述第二电路层之间建立电连续性。 第一表面与第二表面相邻。 至少一个环形延迟电路包括部分地设置在第一电路层上的第一环延迟路径和部分地设置在第二电路层上的第二环延迟路径。 第一环延迟路径和第二环延迟路径形成具有预定测量签名的信号路径。 环形延迟电路将预定测量签名与测试测量签名进行比较。

    WAFER-TO-WAFER ALIGNMENTS
    29.
    发明申请
    WAFER-TO-WAFER ALIGNMENTS 失效
    WAFER-WAFER对准

    公开(公告)号：US20080308948A1

    公开(公告)日：2008-12-18

    申请号：US12198221

    申请日：2008-08-26

    Applicant: Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

    Inventor： Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

    IPC: H01L23/52 ,  H01L21/66

    CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.

    Abstract translation: 用于对准晶片的结构及其操作方法。 该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。 第一和第二半导体晶片经由公共表面彼此直接物理接触。 如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则 包括第一和第二电容耦合结构的第一电容器的电容的至少10-18F的结果。 第一个方向基本上平行于共同的表面。

    PHOTOLITHOGRAPHY MASK WITH PROTECTIVE SILICIDE CAPPING LAYER
    30.
    发明申请
    PHOTOLITHOGRAPHY MASK WITH PROTECTIVE SILICIDE CAPPING LAYER 审中-公开
    具有保护性硅胶覆盖层的光刻胶面板

    公开(公告)号：US20080261121A1

    公开(公告)日：2008-10-23

    申请号：US11738004

    申请日：2007-04-20

    Applicant: Jeffrey Peter Gambino ,  Robert Kenneth Leidy ,  Kirk David Peterson ,  Jed Hickory Rankin ,  Edmund Juris Sprogis

    Inventor： Jeffrey Peter Gambino ,  Robert Kenneth Leidy ,  Kirk David Peterson ,  Jed Hickory Rankin ,  Edmund Juris Sprogis

    IPC: G03C5/00 ,  G03F1/00

    CPC classification number: G03F1/30 ,  G03F1/48 ,  G03F1/54

    Abstract: A photomask and a method of fabricating the photomask. The photomask including: a substrate transparent to a selected wavelength or wavelengths of radiation, the substrate having a top surface and an opposite bottom surface, the substrate having a printable region and a non-printable region; the printable region having first opaque regions raised above the top surface of the substrate adjacent to clear regions, each opaque region of the first opaque regions having sidewalls and opposite top and bottom surfaces, the first opaque regions including a metal; the non-printable region including metal second opaque region raised above the top surface of the substrate, the second opaque region having sidewalls and opposite top and bottom surface, the second opaque regions including the metal; and a conformal protective metal oxide capping layer on top surfaces and sidewalls of the first and second opaque regions. The conformal layer is formed by oxidation.

    Abstract translation: 光掩模和制造光掩模的方法。 所述光掩模包括：对所选择的波长或辐射波长透明的衬底，所述衬底具有顶表面和相对的底表面，所述衬底具有可打印区域和不可打印区域; 所述可印刷区域具有在所述基板的与所述透明区域相邻的顶表面上方的第一不透明区域，所述第一不透明区域的每个不透明区域具有侧壁和相对的顶表面和底表面，所述第一不透明区域包括金属; 所述不可打印区域包括在所述基板的顶表面上方升高的金属第二不透明区域，所述第二不透明区域具有侧壁和相对的顶部和底部表面，所述第二不透明区域包括所述金属; 以及在第一和第二不透明区域的顶表面和侧壁上的共形保护性金属氧化物覆盖层。 保形层通过氧化形成。

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