公开(公告)号：US07925854B2

公开(公告)日：2011-04-12

申请号：US11771241

申请日：2007-06-29

Applicant: HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

Inventor： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G06F12/00

CPC classification number: G06F13/4239 ,  G11C16/08 ,  G11C16/20 ,  G11C2216/30

Abstract: A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.

Abstract translation: 提供了存储器系统结构，其中存储器控制器控制串行互连配置中的存储器件。 存储器控制器具有用于发送存储器命令的输出端口和用于接收用于请求这样的响应的那些存储器命令的存储器响应的输入端口。 每个存储器件包括诸如NAND型闪存，NOR型闪速存储器，随机存取存储器和静态随机存取存储器之类的存储器。 每个存储器命令特定于目标存储器件的存储器类型。 存储器命令和存储器响应的数据路径由互连提供。 给定的存储器命令遍历存储器件以达到其串行互连配置的预期存储器件。 在其接收时，预期的存储器件执行给定的存储器命令，并且如果适当的话，向下一个存储器件发送存储器响应。 存储器响应被传送到存储器控制器。

公开(公告)号：US07923370B2

公开(公告)日：2011-04-12

申请号：US12852082

申请日：2010-08-06

Applicant: Hong Beom Pyeon

Inventor： Hong Beom Pyeon

IPC: H01L21/768

CPC classification number: H01L25/0657 ,  G11C5/02 ,  G11C5/066 ,  G11C16/06 ,  G11C19/00 ,  H01L21/76898 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/00

Abstract: A multi-chip device and method of stacking a plurality substantially identical chips to produce the device are provided. The multi-chip device, or circuit, includes at least one through-chip via providing a parallel connection between signal pads from at least two chips, and at least one through-chip via providing a serial or daisy chain connection between signal pads from at least two chips. Common connection signal pads are arranged symmetrically about a center line of the chip with respect to duplicate common signal pads. Input signal pads are symmetrically disposed about the center line of the chip with respect to corresponding output signal pads. The chips in the stack are alternating flipped versions of the substantially identical chip to provide for this arrangement. At least one serial connection is provided between signal pads of stacked and flipped chips when more than two chips are stacked.

Abstract translation: 提供了堆叠多个基本上相同的芯片以产生该装置的多芯片装置和方法。 多芯片器件或电路包括至少一个穿芯片通孔，其通过提供来自至少两个芯片的信号焊盘之间的并联连接以及至少一个穿芯片通孔，以提供从信号焊盘处的串联或菊花链连接 至少两块芯片。 公共连接信号焊盘相对于重复的公共信号焊盘对称地布置在芯片的中心线上。 输入信号焊盘相对于相应的输出信号焊盘对称地设置在芯片的中心线周围。 堆叠中的芯片是基本上相同的芯片的交替翻转版本，以提供这种布置。 当堆叠超过两个芯片时，至少有一个串行连接提供在堆叠和翻转芯片的信号焊盘之间。

公开(公告)号：US07904639B2

公开(公告)日：2011-03-08

申请号：US11840692

申请日：2007-08-17

Applicant: Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

Inventor： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

IPC: G06F12/00

CPC classification number: G11C7/1045 ,  G06F13/1678 ,  G11C7/10 ,  Y02D10/14

Abstract: A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from the host system to one or more separatable commands interpretable by the at least one memory device. Each command has a modular structure including an address identifier for one of the at least one memory devices and a command identifier representing an operation to be performed by the one of the at least one memory devices. The at least one memory device and the controller are in a series-connection configuration for communication such that only one memory device is in communication with the controller for input into the memory system. The memory system can include a plurality of memory devices connected to a common bus.

Abstract translation: 包括存储器系统和存储器控制器的系统连接到主机系统。 存储器系统具有存储数据的至少一个存储器件。 控制器将来自主机系统的请求转换成由至少一个存储设备可解释的一个或多个可分离命令。 每个命令具有模块化结构，其包括用于至少一个存储器设备中的一个的地址标识符和表示由至少一个存储器设备之一执行的操作的命令标识符。 至少一个存储器设备和控制器处于用于通信的串联连接配置中，使得仅一个存储器设备与控制器通信以输入到存储器系统中。 存储器系统可以包括连接到公共总线的多个存储器件。

公开(公告)号：US20110037148A1

公开(公告)日：2011-02-17

申请号：US12701122

申请日：2010-02-05

Applicant: Hong Beom Pyeon

Inventor： Hong Beom Pyeon

IPC: H01L23/544 ,  H01L21/78 ,  H01L21/50 ,  H01L23/48

CPC classification number: H01L21/82 ,  H01L23/49805 ,  H01L24/05 ,  H01L24/24 ,  H01L24/37 ,  H01L24/40 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/24145 ,  H01L2224/371 ,  H01L2224/37599 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/84

Abstract: An integrated circuit apparatus is provided with package-level connectivity, between internal electronic circuitry thereof and contact points on a package substrate thereof, without requiring top metal pads or bonding wires.

Abstract translation: 集成电路设备具有封装级连接性，其内部电子电路与其封装衬底上的接触点之间，而不需要顶部金属焊盘或接合线。

公开(公告)号：US20110032784A1

公开(公告)日：2011-02-10

申请号：US12564492

申请日：2009-09-22

Applicant: Hong-Beom PYEON

Inventor： Hong-Beom PYEON

IPC: G11C8/08 ,  G11C7/00

CPC classification number: G11C8/08 ,  G11C7/20

Abstract: A semiconductor memory circuit, comprising: a memory array, the memory array including a plurality of wordlines each connected to a respective row of cells and a plurality of bitlines each connected to a respective column of cells. The semiconductor memory circuit also comprises at least one row decoder for selecting a group of wordlines within the plurality of wordlines; and a plurality of driver circuits for driving the plurality of bitlines respectively and setting the cells connected to the group of wordlines to a predetermined logic state. Also, a method for presetting at least part of a memory array, the memory array comprising a plurality of wordlines each connected to a respective row of cells. The method comprises selecting a group of wordlines within the plurality of wordlines; and simultaneously setting memory cells connected to the group of wordlines to a predetermined logic state.

Abstract translation: 一种半导体存储器电路，包括：存储器阵列，所述存储器阵列包括各自连接到相应行单元的多个字线和多个位线，每个位线连接到相应的单元格列。 所述半导体存储器电路还包括用于选择所述多个字线内的一组字线的至少一个行解码器; 以及多个驱动电路，用于分别驱动多个位线，并将连接到该组字线的单元设置为预定的逻辑状态。 此外，一种用于预设存储器阵列的至少一部分的方法，所述存储器阵列包括多个字线，每个字线连接到相应的单元行。 该方法包括选择多个字线内的一组字线; 并且将连接到该字线组的存储单元同时设置为预定的逻辑状态。

公开(公告)号：US20100327923A1

公开(公告)日：2010-12-30

申请号：US12823472

申请日：2010-06-25

Applicant: Hong Beom PYEON ,  Hunsam JUNG ,  Peter B. GILLINGHAM

Inventor： Hong Beom PYEON ,  Hunsam JUNG ,  Peter B. GILLINGHAM

IPC: H03L7/00

CPC classification number: G06F1/08 ,  G06F3/0676 ,  G06F12/0246 ,  G06F13/1689 ,  G11C7/04

Abstract: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. A configurable clock controller receives a system clock and generates a memory clock having a frequency that is a predetermined ratio of the system clock. The system clock frequency is dynamically variable between a maximum and a minimum value, and the ratio of the memory clock frequency relative to the system clock frequency is set by loading a frequency register with a Frequency Divide Ratio (FDR) code any time during operation of the composite memory device. In response to the FDR code, the configurable clock controller changes the memory clock frequency.

Abstract translation: 一种复合存储器件，包括分立存储器件和用于控制分立存储器件的桥接器件。 可配置的时钟控制器接收系统时钟并产生具有系统时钟的预定比率的频率的存储器时钟。 系统时钟频率在最大和最小值之间动态变化，并且存储器时钟频率相对于系统时钟频率的比率通过在运行期间的任何时间加载具有频率分频比（FDR）代码的频率寄存器来设置 复合存储器件。 响应于FDR代码，可配置的时钟控制器改变存储器时钟频率。

公开(公告)号：US20100306569A1

公开(公告)日：2010-12-02

申请号：US12851884

申请日：2010-08-06

Applicant: Hong Beom Pyeon

Inventor： Hong Beom Pyeon

IPC: G06F1/04

CPC classification number: G06F13/4291 ,  B60R1/0617

Abstract: A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory devices has multiple independent serial ports for receiving and transmitting data. The memory controller a device address (DA) or ID number for designating a device that executes a command. Data contained in the command sent by the memory controller is captured by an individual link control circuit, in response to internally generated clock with appropriate latencies. The captured data is written into a corresponding memory bank. The data stored in one of a plurality of memory banks of one memory device is read in accordance with the addresses issued by the memory controller. The read data is propagated from the memory device through the series-connected memory devices to the memory controller.

Abstract translation: 系统包括与存储器控制器通信的存储器控​​制器和串联连接的多个存储器件。 每个存储器件具有用于接收和发送数据的多个独立串行端口。 存储器控制器用于指定执行命令的设备的设备地址（DA）或ID号。 由存储器控制器发送的命令中包含的数据由单独的链路控制电路捕获，以响应具有适当延迟的内部生成的时钟。 捕获的数据被写入对应的存储体。 根据由存储器控制器发出的地址来读取存储在一个存储器件的多个存储器组之一中的数据。 读取的数据从存储器件通过串联连接的存储器件传播到存储器控制器。

公开(公告)号：US20100297812A1

公开(公告)日：2010-11-25

申请号：US12852082

申请日：2010-08-06

Applicant: Hong Beom PYEON

Inventor： Hong Beom PYEON

IPC: H01L21/50

CPC classification number: H01L25/0657 ,  G11C5/02 ,  G11C5/066 ,  G11C16/06 ,  G11C19/00 ,  H01L21/76898 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/00

Abstract: A multi-chip device and method of stacking a plurality substantially identical chips to produce the device are provided. The multi-chip device, or circuit, includes at least one through-chip via providing a parallel connection between signal pads from at least two chips, and at least one through-chip via providing a serial or daisy chain connection between signal pads from at least two chips. Common connection signal pads are arranged symmetrically about a center line of the chip with respect to duplicate common signal pads. Input signal pads are symmetrically disposed about the center line of the chip with respect to corresponding output signal pads. The chips in the stack are alternating flipped versions of the substantially identical chip to provide for this arrangement. At least one serial connection is provided between signal pads of stacked and flipped chips when more than two chips are stacked.

Abstract translation: 提供了堆叠多个基本上相同的芯片以产生该装置的多芯片装置和方法。 多芯片器件或电路包括至少一个穿芯片通孔，其通过提供来自至少两个芯片的信号焊盘之间的并联连接以及至少一个穿芯片通孔，以提供从信号焊盘处的串联或菊花链连接 至少两块芯片。 公共连接信号焊盘相对于重复的公共信号焊盘对称地布置在芯片的中心线上。 输入信号焊盘相对于相应的输出信号焊盘对称地设置在芯片的中心线周围。 堆叠中的芯片是基本上相同的芯片的交替翻转版本，以提供这种布置。 当堆叠超过两个芯片时，至少有一个串行连接提供在堆叠和翻转芯片的信号焊盘之间。

公开(公告)号：US07839689B2

公开(公告)日：2010-11-23

申请号：US12115784

申请日：2008-05-06

Applicant: Hong Beom Pyeon ,  Jin-Ki Kim

Inventor： Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C16/04

CPC classification number: G11C16/30 ,  G11C5/145 ,  G11C5/147 ,  H02M3/073

Abstract: Power supplies in flash memory devices are disclosed. A first section of a flash memory device includes non-volatile memory for storing data. A second section of the flash memory device includes at least first and second pumping circuits. The first pumping circuit receives a first voltage and produces, at an output of the first pumping circuit, a second voltage at a second voltage level that is higher than the first voltage level. The second pumping circuit has an input coupled to the first pumping circuit output for cooperatively employing the first pumping circuit to pump up from a voltage greater than the first voltage to produce a third voltage at a third voltage level that is higher than the second voltage level.

Abstract translation: 公开了闪存设备中的电源。 闪存器件的第一部分包括用于存储数据的非易失性存储器。 闪存器件的第二部分至少包括第一和第二泵浦电路。 第一泵送电路接收第一电压，并且在第一泵送电路的输出处产生高于第一电压电平的第二电压电平的第二电压。 第二泵浦电路具有耦合到第一泵浦电路输出的输入端，用于协同地采用第一泵浦电路从大于第一电压的电压泵浦，以产生高于第二电压电平的第三电压电平的第三电压 。

公开(公告)号：US20100268853A1

公开(公告)日：2010-10-21

申请号：US12784238

申请日：2010-05-20

Applicant: HakJune OH ,  Hong Beom Pyeon ,  Jin-Ki Kim

Inventor： HakJune OH ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G06F13/28 ,  G06F3/00

CPC classification number: G11C7/10 ,  G06F13/1689

Abstract: A system controller communicates with devices in a serial interconnection. The system controller sends a read command, a device address identifying a target device in the serial interconnection and a memory location. The target device responds to the read command to read data in the location identified by the memory location. Read data is provided as an output signal that is transmitted from a last device in the serial interconnection to a data receiver of the controller. The data receiver establishes acquisition instants relating to clocks in consideration of a total flow-through latency in the serial interconnection. Where each device has a clock synchronizer, a propagated clock signal through the serial interconnection is used for establishing the acquisition instants. The read data is latched in response to the established acquisition instants in consideration of the flow-through latency, valid data is latched in the data receiver.

Abstract translation: 系统控制器与串行互连中的设备通信。 系统控制器发送读取命令，标识串行互连中的目标设备的设备地址和存储器位置。 目标设备响应读取命令以读取由存储器位置识别的位置中的数据。 读取数据被提供为从串行互连中的最后一个设备发送到控制器的数据接收器的输出信号。 考虑到串行互连中的总流通延迟，数据接收器建立与时钟有关的采集时刻。 在每个设备具有时钟同步器的情况下，通过串行互连的传播时钟信号用于建立采集时刻。 考虑到流通延迟，响应于建立的采集时刻来读取数据被锁存，有效数据被锁存在数据接收器中。