公开(公告)号：US07091758B2

公开(公告)日：2006-08-15

申请号：US10834851

申请日：2004-04-30

Applicant: Ki-Chul Chun ,  Jae-Yoon Sim

Inventor： Ki-Chul Chun ,  Jae-Yoon Sim

IPC: H03K17/22

CPC classification number: H03K3/356008 ,  H03K17/223

Abstract: A semiconductor integrated circuit may include an internal circuit, and a power-on reset circuit for generating a power-on reset signal to initialize the internal circuit at a power-on. At the power-on, the power-on reset circuit delays a transition of the power-on reset signal from a first level to a second level until a given time duration after the power supply voltage reaches a detection voltage.

Abstract translation: 半导体集成电路可以包括内部电路和用于产生上电复位信号的上电复位电路，以在通电时初始化内部电路。 在上电时，上电复位电路延迟上电复位信号从第一电平转换到第二电平，直到电源电压达到检测电压之后的给定持续时间。

公开(公告)号：US06545923B2

公开(公告)日：2003-04-08

申请号：US09901785

申请日：2001-07-09

Applicant: Jae-Yoon Sim ,  Jei-Hwan Yoo

Inventor： Jae-Yoon Sim ,  Jei-Hwan Yoo

IPC: G11C808

CPC classification number: G11C11/4085 ,  G11C8/08

Abstract: A memory device utilizing a negatively biased word line scheme diverts word line discharge current from the negative voltage source during a precharge operation, thereby reducing voltage fluctuations and current consumption from the negative voltage source. A main word line, sub-word line, word line enable signal, or other type of word line is coupled to the negative voltage source during a precharge operation. The word line is also coupled to a second power supply during the precharge operation, and then uncoupled from the second power supply after most of the word line discharge current has been diverted. The negative voltage source can then discharge and maintain the word line at a negative bias.

Abstract translation: 利用负偏置字线方案的存储器件在预充电操作期间从负电压源转移字线放电电流，从而降低来自负电压源的电压波动和电流消耗。 在预充电操作期间，主字线，子字线，字线使能信号或其它类型的字线耦合到负电压源。 在预充电操作期间，字线还耦合到第二电源，然后在大部分字线放电电流被转移之后与第二电源分离。 然后，负电压源可以以负偏压放电并维持字线。

公开(公告)号：US06424578B1

公开(公告)日：2002-07-23

申请号：US09748350

申请日：2000-12-22

Applicant: Jae-Yoon Sim ,  Jei-Hwan Yoo

Inventor： Jae-Yoon Sim ,  Jei-Hwan Yoo

IPC: G11C700

Abstract: A voltage detecting circuit includes a first voltage generator that provides a reference voltage, a second voltage generator that provides a comparison voltage in response to a boosted voltage, and a differential amplifier that provides an amplified difference signal to generate a voltage level detection signal in response to a voltage difference between the reference voltage and the comparison voltage. A bypass circuit is coupled to the amplified signal to detect a target VPP level suitable for a test mode by providing a current path in response to the comparison voltage when the comparison voltage reaches a predetermined level. The voltage detecting circuit thereby allows a precise and stable detecting operation to be performed regardless of the operation mode or process or temperature variations.

公开(公告)号：US08305248B2

公开(公告)日：2012-11-06

申请号：US12795221

申请日：2010-06-07

Applicant: Seon Kyoo Lee ,  Jae Yoon Sim

Inventor： Seon Kyoo Lee ,  Jae Yoon Sim

IPC: H03M1/50

CPC classification number: G04F10/005

Abstract: A time-to-digital converter includes a phase-difference enhancement section configured to receive first and second input signals having a reference phase difference Δt, and to output first and second output signals having an enhanced phase difference; and a comparison section configured to receive the first and second output signals, to compare a phase difference between the first and second output signals with a reference delay time τ, and to output a comparison signal. The time-to-digital converter has a high resolution. That is to say, the time-to-digital converter has a resolution less than the minimum phase delay time of a delay element, which is obtainable in a corresponding semiconductor process.

Abstract translation: 时间数字转换器包括相位差增强部分，被配置为接收具有参考相位差Dgr; t的第一和第二输入信号，并且输出具有增强的相位差的第一和第二输出信号; 以及比较部，被配置为接收第一和第二输出信号，以将第一和第二输出信号之间的相位差与参考延迟时间τ进行比较，并输出比较信号。 时间 - 数字转换器具有高分辨率。 也就是说，时间 - 数字转换器具有小于延迟元件的最小相位延迟时间的分辨率，其可以在相应的半导体处理中获得。

公开(公告)号：US07705644B2

公开(公告)日：2010-04-27

申请号：US12028936

申请日：2008-02-11

Applicant: Ho-young Kim ,  Dong-bee Jang ,  Jae-yoon Sim ,  Young-sang Kim

Inventor： Ho-young Kim ,  Dong-bee Jang ,  Jae-yoon Sim ,  Young-sang Kim

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/10

Abstract: A broadband multi-phase output delay locked loop (DLL) circuit can be operated in a wide range of frequencies and generate various phases. Unlike conventional voltage control delay lines in which delay cells are connected in series, the DLL circuit utilizes a delay matrix in which a resistant network is used so that the number of delay cells connected in series is reduced, various phases can be outputted, and a delay interval error (phase error) due to the resistant network is minimized. The current of the delay cells is controlled so that the delay cells in the delay matrix can operate in a wide range of frequencies, and load capacitance values of capacitors connected in parallel in the delay cells can be controlled.

Abstract translation: 宽带多相输出延迟锁定环（DLL）电路可以在宽频率范围内工作，并产生各种相位。 与其中延迟单元串联连接的常规电压控制延迟线不同，DLL电路利用其中使用电阻网络的延迟矩阵，使得串联连接的延迟单元的数量减少，可以输出各种相位，并且 由于抵抗网络导致的延迟间隔误差（相位误差）被最小化。 控制延迟单元的电流，使得延迟矩阵中的延迟单元可以在宽的频率范围内工作，并且可以控制在延迟单元中并联连接的电容器的负载电容值。

公开(公告)号：US20080191765A1

公开(公告)日：2008-08-14

申请号：US12028936

申请日：2008-02-11

Applicant: Ho-young KIM ,  Dong-bee JANG ,  Jae-yoon SIM ,  Young-sang KIM

Inventor： Ho-young KIM ,  Dong-bee JANG ,  Jae-yoon SIM ,  Young-sang KIM

IPC: H03L7/00 ,  G11C5/14 ,  G05F3/16

CPC classification number: H03L7/0812 ,  H03L7/10

Abstract: A broadband multi-phase output delay locked loop (DLL) circuit can be operated in a wide range of frequencies and generate various phases. Unlike conventional voltage control delay lines in which delay cells are connected in series, the DLL circuit utilizes a delay matrix in which a resistant network is used so that the number of delay cells connected in series is reduced, various phases can be outputted, and a delay interval error (phase error) due to the resistant network is minimized. The current of the delay cells is controlled so that the delay cells in the delay matrix can operate in a wide range of frequencies, and load capacitance values of capacitors connected in parallel in the delay cells can be controlled.

Abstract translation: 宽带多相输出延迟锁定环（DLL）电路可以在宽频率范围内工作，并产生各种相位。 与其中延迟单元串联连接的常规电压控制延迟线不同，DLL电路利用其中使用电阻网络的延迟矩阵，使得串联连接的延迟单元的数量减少，可以输出各种相位，并且 由于抵抗网络导致的延迟间隔误差（相位误差）被最小化。 控制延迟单元的电流，使得延迟矩阵中的延迟单元可以在宽的频率范围内工作，并且可以控制在延迟单元中并联连接的电容器的负载电容值。

公开(公告)号：US07333378B2

公开(公告)日：2008-02-19

申请号：US11060308

申请日：2005-02-18

Applicant: Jae-Yoon Sim

Inventor： Jae-Yoon Sim

IPC: G11C7/00

CPC classification number: G11C11/4094 ,  G11C7/12 ,  G11C2207/005 ,  G11C2207/2227

Abstract: A semiconductor memory device having a shared sense amplifier architecture includes a bitline equalizing voltage generator, which recycles a boost voltage to generate bitline equalizing voltage. The bitline equalizing voltage is used to generate signals for activating bitline equalizing circuits to precharge the bitlines of at least one of the first and second memory block with a bitline precharge voltage, when the memory block is not currently selected for a data operation. The bitline equalizing voltage generator may be configured to recycle the boost voltage that was used to generate a bitline isolation signal or a wordline drive signal.

Abstract translation: 具有共享读出放大器架构的半导体存储器件包括位线均衡电压发生器，其再循环升压电压以产生位线均衡电压。 位线均衡电压用于产生用于激活位线均衡电路的信号，以便当存储器块当前未被选择用于数据操作时，用位线预充电电压对第一和第二存储器块中的至少一个的位线预充电。 位线均衡电压发生器可以被配置为回收用于产生位线隔离信号或字线驱动信号的升压电压。

公开(公告)号：US07113436B2

公开(公告)日：2006-09-26

申请号：US10731841

申请日：2003-12-09

Applicant: Seung-hoon Lee ,  Jae-yoon Sim

Inventor： Seung-hoon Lee ,  Jae-yoon Sim

IPC: G11C7/02

CPC classification number: G11C7/062

Abstract: Provided is a circuit for use in a semiconductor memory optimized to improve data read ability at low supply voltages. Circuit includes a direct sense AMP circuit, an input/output gate circuit, and an operation control unit. The direct sense AMP circuit transmits read data loaded in a bit line pair including first and second bit lines to a data input/output pair including first and second data input/output lines in response to a read command signal. The input/output gate circuit which, in response to a read/write signal, also passes the read data loaded in the bit line pair directly to the data input/output line pair, and passes write data loaded in the data input/output line pair directly to the bit line pair. The operation control unit which, in response to a column address signal and a write command, generates the read command signal and the read/write signal to turn ON both the direct sense AMP circuit and the input/output gate circuit in a data read operation, or to turn ON the input/output gate circuit and turn OFF the direct sense AMP circuit in a data write operation.

Abstract translation: 提供了一种用于半导体存储器中的电路，其被优化以在低电源电压下提高数据读取能力。 电路包括直接感测AMP电路，输入/输出门电路和操作控制单元。 直接感测放大器电路响应于读取命令信号，将包括第一和第二位线的位线对中的读取数据传输到包括第一和第二数据输入/输出线的数据输入/输出对。 输入/输出门电路响应于读/写信号也将加载在位线对中的读数据直接传送到数据输入/输出线对，并将加载在数据输入/输出线 直接对位线对。 操作控制单元，响应于列地址信号和写命令，产生读指令信号和读/写信号，以在数据读操作中接通直接检测AMP电路和输入/输出门电路 或者在数据写入操作中打开输入/输出门电路并关闭直接感测AMP电路。

公开(公告)号：US20050195669A1

公开(公告)日：2005-09-08

申请号：US11060308

申请日：2005-02-18

Applicant: Jae-Yoon Sim

Inventor： Jae-Yoon Sim

IPC: G11C7/12 ,  G11C11/4094 ,  G11C7/00

CPC classification number: G11C11/4094 ,  G11C7/12 ,  G11C2207/005 ,  G11C2207/2227

Abstract: A semiconductor memory device having a shared sense amplifier architecture includes a bitline equalizing voltage generator, which recycles a boost voltage to generate bitline equalizing voltage. The bitline equalizing voltage is used to generate signals for activating bitline equalizing circuits to precharge the bitlines of at least one of the first and second memory block with a bitline precharge voltage, when the memory block is not currently selected for a data operation. The bitline equalizing voltage generator may be configured to recycle the boost voltage that was used to generate a bitline isolation signal or a wordline drive signal.

Abstract translation: 具有共享读出放大器架构的半导体存储器件包括位线均衡电压发生器，其再循环升压电压以产生位线均衡电压。 位线均衡电压用于产生用于激活位线均衡电路的信号，以便当存储器块当前未被选择用于数据操作时，用位线预充电电压对第一和第二存储器块中的至少一个的位线预充电。 位线均衡电压发生器可以被配置为回收用于产生位线隔离信号或字线驱动信号的升压电压。

公开(公告)号：US06798709B2

公开(公告)日：2004-09-28

申请号：US10384630

申请日：2003-03-11

Applicant: Jae-Yoon Sim ,  Dong-Il Seo

Inventor： Jae-Yoon Sim ,  Dong-Il Seo

IPC: G11C700

CPC classification number: G11C11/4074 ,  G11C2207/2227 ,  H02M2001/0032 ,  Y02B70/16 ,  Y10T307/696

Abstract: A plurality of internal circuits of a memory device are operable at first and second internal voltages, where the first internal voltage is less than the second internal voltage. A first power port of the memory device receives a first power supply voltage, and a second power port of the memory device receives a second power supply voltage, where the first power supply voltage is less than the second power supply voltage. An internal voltage generation circuit of the memory device is selectively operable in either a first mode in which the second internal voltage is generated from the first power supply voltage, or a second mode in which the second internal voltage is generated from the second power supply voltage.

Abstract translation: 存储器件的多个内部电路可在第一和第二内部电压下操作，其中第一内部电压小于第二内部电压。 存储器件的第一电源端口接收第一电源电压，并且存储器件的第二电源端口接收第二电源电压，其中第一电源电压小于第二电源电压。 存储器件的内部电压产生电路可选择性地在第一模式中工作，其中从第一电源电压产生第二内部电压，或第二模式，其中从第二电源电压产生第二内部电压 。