公开(公告)号：US07544565B2

公开(公告)日：2009-06-09

申请号：US11642198

申请日：2006-12-20

Applicant: Dong-Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

Inventor： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

IPC: H01L21/8247

CPC classification number: H01L27/105 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

Abstract: Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

Abstract translation: 形成半导体器件的方法包括在具有有源区和器件隔离区的半导体衬底上形成沟槽掩模图案。 使用沟槽掩模图案作为扩散掩模进行热氧化处理，以形成限定有源区的凸上表面的热氧化层。 使用沟槽掩模图案作为蚀刻掩模蚀刻热氧化物层和半导体衬底，以形成限定有源区的凸上表面的沟槽。 去除沟槽掩模图案以露出活性区域的凸上表面。 形成在有源区域上延伸的栅极图案。

公开(公告)号：US07521348B2

公开(公告)日：2009-04-21

申请号：US11871877

申请日：2007-10-12

Applicant: Sung-Hyun Kwon ,  Jae-Hwang Sim ,  Dong-Hwa Kwak ,  Joo-Young Kim

Inventor： Sung-Hyun Kwon ,  Jae-Hwang Sim ,  Dong-Hwa Kwak ,  Joo-Young Kim

IPC: H01L21/44

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A method for fabricating a semiconductor device having fine contact holes is exemplarily disclosed. The method includes forming an isolation layer defining active regions on a semiconductor substrate. An interlayer dielectric layer is formed on the semiconductor substrate having the isolation layer. First molding patterns are formed on the interlayer dielectric layer. Second molding patterns positioned between the first molding patterns and spaced apart therefrom are also formed. A mask pattern surrounding sidewalls of the first and second molding patterns is formed. Openings are formed by removing the first and second molding patterns. Contact holes are formed by etching the interlayer dielectric layer using the mask pattern as an etching mask.

Abstract translation: 示例性地公开了一种制造具有精细接触孔的半导体器件的方法。 该方法包括在半导体衬底上形成限定有源区的隔离层。 在具有隔离层的半导体衬底上形成层间电介质层。 在层间电介质层上形成第一成型图案。 还形成了位于第一模制图案之间并与之间隔开的第二模制图案。 形成围绕第一和第二模制图案的侧壁的掩模图案。 通过去除第一和第二模制图案形成开口。 通过使用掩模图案作为蚀刻掩模蚀刻层间电介质层来形成接触孔。

公开(公告)号：US20080096391A1

公开(公告)日：2008-04-24

申请号：US11871877

申请日：2007-10-12

Applicant: Sung-Hyun KWON ,  Jae-Hwang SIM ,  Dong-Hwa KWAK ,  Joo-Young KIM

Inventor： Sung-Hyun KWON ,  Jae-Hwang SIM ,  Dong-Hwa KWAK ,  Joo-Young KIM

IPC: H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A method for fabricating a semiconductor device having fine contact holes is exemplary disclosed. The method includes forming an isolation layer defining active regions on a semiconductor substrate. An interlayer dielectric layer is formed on the semiconductor substrate having the isolation layer. First molding patterns are formed on the interlayer dielectric layer. Second molding patterns positioned between the first molding patterns and spaced apart therefrom are also formed. A mask pattern surrounding sidewalls of the first and second molding patterns is formed. Openings are formed by removing the first and second molding patterns. Contact holes are formed by etching the interlayer dielectric layer using the mask pattern as an etching mask.

Abstract translation: 公开了一种制造具有精细接触孔的半导体器件的方法。 该方法包括在半导体衬底上形成限定有源区的隔离层。 在具有隔离层的半导体衬底上形成层间电介质层。 在层间电介质层上形成第一成型图案。 还形成了位于第一模制图案之间并与之间隔开的第二模制图案。 形成围绕第一和第二模制图案的侧壁的掩模图案。 通过去除第一和第二模制图案形成开口。 通过使用掩模图案作为蚀刻掩模蚀刻层间电介质层来形成接触孔。

公开(公告)号：US20140167290A1

公开(公告)日：2014-06-19

申请号：US14186617

申请日：2014-02-21

Applicant: Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

Inventor： Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

IPC: H01L23/528

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823456 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

Abstract translation: 在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。 掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是 位于。 模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。 间隔层设置在第一区域和第二区域中的模具掩模图案上。 执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。 使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征 。

公开(公告)号：US08368182B2

公开(公告)日：2013-02-05

申请号：US12573535

申请日：2009-10-05

Applicant: Young-ho Lee ,  Jae-hwang Sim ,  Young-seop Rah

Inventor： Young-ho Lee ,  Jae-hwang Sim ,  Young-seop Rah

IPC: H01L29/06

CPC classification number: H01L27/105 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76229 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11526

Abstract: Provided are a method of forming patterns for a semiconductor device in which a pattern density is doubled by performing double patterning in a part of a device region while patterns having different widths are being simultaneously formed, and a semiconductor device having a structure to which the method is easily applicable. The semiconductor device includes a plurality of line patterns extending parallel to each other in a first direction. A plurality of first line patterns are alternately selected in a second direction from among the plurality of line patterns and each have a first end existing near the first side. A plurality of second line patterns are alternately selected in the second direction from among the plurality of line patterns and each having a second end existing near the first side. The first line patterns alternate with the second line patterns and the first end of each first line pattern is farther from the first side than the second end of each second line pattern.

Abstract translation: 提供了一种通过在同时形成具有不同宽度的图案的同时在器件区域的一部分中进行双重图案化来形成图案密度加倍的半导体器件的图案的方法，以及具有该方法的结构的半导体器件 很容易适用。 半导体器件包括在第一方向上彼此平行延伸的多条线图案。 多个第一线图案在多个线条图案之间沿第二方向交替选择，并且每个第一线图案具有靠近第一侧的第一端。 在多个线图案之间沿第二方向交替地选择多个第二线图案，并且每个具有在第一侧附近存在的第二端。 第一线图案与第二线图案交替，并且每个第一线图案的第一端距离每第二线图案的第二端更远离第一侧。

公开(公告)号：US08173549B2

公开(公告)日：2012-05-08

申请号：US12477468

申请日：2009-06-03

Applicant: Young-ho Lee ,  Jae-hwang Sim ,  Jae-kwan Park ,  Jong-min Lee ,  Mo-seok Kim ,  Hyon-woo Kim

Inventor： Young-ho Lee ,  Jae-hwang Sim ,  Jae-kwan Park ,  Jong-min Lee ,  Mo-seok Kim ,  Hyon-woo Kim

IPC: H01L21/302

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/0207 ,  H01L27/1052

Abstract: A first mask layer pattern including a plurality of parallel line portions is formed on an etch target layer on a semiconductor substrate. A sacrificial layer is formed on the first mask layer pattern and portions of the etch target layer between the parallel line portions of the first mask layer pattern. A second mask layer pattern is formed on the sacrificial layer, the second mask layer pattern including respective parallel lines disposed between respective adjacent ones of the parallel line portions of the first mask layer pattern, wherein adjacent line portions of the first mask layer pattern and the second mask layer pattern are separated by the sacrificial layer. A third mask layer pattern is formed including first and second portions covering respective first and second ends of the line portions of the first mask layer pattern and the second mask layer pattern and having an opening at the line portions of the first and second mask layer patterns between the first and second ends. The sacrificial layer and the etch target layer are etched using the third mask layer pattern, the first mask layer pattern and the second mask layer pattern as a mask to thereby form a plurality of parallel trenches in the etch target layer between the line portions of the first and second mask layer patterns. Conductive lines may be formed in the trenches.

Abstract translation: 在半导体衬底上的蚀刻目标层上形成包括多个平行线部分的第一掩模层图案。 在第一掩模层图案和第一掩模层图案的平行线部分之间的蚀刻目标层的部分上形成牺牲层。 第二掩模层图案形成在牺牲层上，第二掩模层图案包括设置在第一掩模层图案的相邻的平行线部分之间的相应的平行线，其中第一掩模层图案和 第二掩模层图案由牺牲层分离。 形成第三掩模层图案，其包括覆盖第一掩模层图案和第二掩模层图案的线部分的相应第一和第二端的第一和第二部分，并且在第一和第二掩模层图案的线部分处具有开口 在第一和第二端之间。 使用第三掩模层图案，第一掩模层图案和第二掩模层图案作为掩模来蚀刻牺牲层和蚀刻目标层，从而在蚀刻目标层中形成多个平行的沟槽 第一和第二掩模层图案。 可以在沟槽中形成导电线。

公开(公告)号：US08142986B2

公开(公告)日：2012-03-27

申请号：US12192430

申请日：2008-08-15

Applicant: Jae-hwang Sim ,  Sang-yong Park ,  Young-ho Lee

Inventor： Jae-hwang Sim ,  Sang-yong Park ,  Young-ho Lee

IPC: G03F7/20

CPC classification number: H01L27/11573 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11575

Abstract: A method of forming fine patterns of a semiconductor device, in which a plurality of conductive lines formed in a cell array region are integrally formed with contact pads for connecting the conductive lines to a peripheral circuit. In this method, a plurality of mold mask patterns, each including a first portion extending in a first direction and a second portion which is integrally formed with the first portion and extends in a second direction, are formed within a cell block on a substrate comprising a film which is to be etched. A first mask layer covering sidewalls and an upper surface of each of the plurality of mold mask patterns is formed on the substrate. First mask patterns are formed by partially removing the first mask layer so that a first area of the first mask layer remains and a second area of the first mask layer is removed. The first area of the first mask layer covers sidewalls of adjacent mold mask patterns from among the plurality of mold mask patterns by being located between the adjacent mold mask patterns, and the second area of the first mask layer covers portions of the sidewalls of the plurality of mold mask patterns, the portions corresponding to an outermost sidewall of a mold mask pattern block.

Abstract translation: 一种形成半导体器件的精细图案的方法，其中形成在单元阵列区域中的多个导线与用于将导线连接到外围电路的接触焊盘一体地形成。 在该方法中，在基板上形成多个模具掩模图案，每个模具掩模图案包括沿第一方向延伸的第一部分和与第一部分整体形成并在第二方向上延伸的第二部分， 要蚀刻的薄膜。 在基板上形成覆盖多个模具掩模图案中的每一个的侧壁和上表面的第一掩模层。 通过部分去除第一掩模层形成第一掩模图案，使得第一掩模层的第一区域保留，并且去除第一掩模层的第二区域。 第一掩模层的第一区域通过位于相邻的模具掩模图案之间而覆盖多个模具掩模图案中的相邻模具掩模图案的侧壁，并且第一掩模层的第二区域覆盖多个模具掩模图案的侧壁的部分 的模具掩模图案，其对应于模具掩模图案块的最外侧壁的部分。

公开(公告)号：US20110136340A1

公开(公告)日：2011-06-09

申请号：US12904363

申请日：2010-10-14

Applicant: Jae-Hwang Sim ,  Yoon-Moon PARK ,  Keon-Soo KIM ,  Min-Sung SONG ,  Young-Ho LEE

Inventor： Jae-Hwang Sim ,  Yoon-Moon PARK ,  Keon-Soo KIM ,  Min-Sung SONG ,  Young-Ho LEE

IPC: H01L21/3213 ,  H01L21/308

CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  Y10S438/947

Abstract: A method of fabricating a semiconductor device facilitates the forming of a conductive pattern of features having different widths. A conductive layer is formed on a substrate, and a mask layer is formed on the conductive layer. First spaced apart patterns are formed on the mask layer and a second pattern including first and second parallel portion is formed beside the first patterns on the mask layer. First auxiliary masks are formed over ends of the first patterns, respectively, and a second auxiliary mask is formed over the second pattern as spanning the first and second portions of the second pattern. The mask layer is then etched to form first mask patterns below the first patterns and a second mask pattern below the second pattern. The first and second patterns and the first and second auxiliary masks are removed. The conductive layer is then etched using the first and second mask patterns as an etch mask.

Abstract translation: 制造半导体器件的方法有助于形成具有不同宽度的特征的导电图案。 在基板上形成导电层，在导电层上形成掩模层。 在掩模层上形成第一间隔开的图案，并且在掩模层上的第一图案旁边形成包括第一和第二平行部分的第二图案。 第一辅助掩模分别形成在第一图案的端部上，并且第二辅助掩模形成在第二图案上，跨越第二图案的第一和第二部分。 然后蚀刻掩模层以在第一图案下方形成第一掩模图案，并在第二图案下方形成第二掩模图案。 去除第一和第二图案以及第一和第二辅助掩模。 然后使用第一和第二掩模图案作为蚀刻掩模蚀刻导电层。

公开(公告)号：US20110032763A1

公开(公告)日：2011-02-10

申请号：US12909223

申请日：2010-10-21

Applicant: Dong-Hwa Kwak ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Jin-Ho Kim ,  Ki-Nam Kim

Inventor： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Jin-Ho Kim ,  Ki-Nam Kim

IPC: G11C16/04

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

Abstract: In some embodiments, a semiconductor device includes first bit lines connected to respective first contacts. Spacers are disposed on sidewalls of the first bit lines. A second bit line is self-alignedly disposed between adjacent spacers, and a second contact is self-aligned with and connected to the second bit line.

Abstract translation: 在一些实施例中，半导体器件包括连接到相应的第一触点的第一位线。 间隔件设置在第一位线的侧壁上。 第二位线自相对地布置在相邻间隔件之间，并且第二触点与第二位线自对准并连接到第二位线。

公开(公告)号：US20090321931A1

公开(公告)日：2009-12-31

申请号：US12313234

申请日：2008-11-18

Applicant: Young-ho Lee ,  Jae-hwang Sim ,  Jae-Kwan Park

Inventor： Young-ho Lee ,  Jae-hwang Sim ,  Jae-Kwan Park

IPC: H01L23/52

CPC classification number: H01L21/76897 ,  H01L21/76831 ,  H01L21/76883 ,  H01L23/485 ,  H01L27/115 ,  H01L27/11517 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a method of manufacturing the semiconductor device maintain an insulating distance between contact plugs and wiring lines formed on the contact plugs by using an etch mask pattern for forming contact holes. The device comprises a substrate comprising a plurality of conductive areas; an inter-layer insulating layer on the substrate having a plurality of contact holes through which the conductive areas are exposed; a first insulating layer covering the top surface of the inter-layer insulating layer; a plurality of contact plugs respectively connected to the plurality of conductive areas through the plurality of contact holes, the plurality of contact plugs having top surfaces a distance from each of which to a top surface of the substrate is less than a distance from the top surface of the inter-layer insulating layer to the top surface of the substrate; a plurality of ring-shaped insulating spacers covering inner sidewalls of the inter-layer insulating layer, inner sidewalls of the first insulating layer, and outer edge areas of top surfaces of the contact plugs so as to expose center areas of the top surfaces of the contact plugs in the contact holes; and a plurality of wiring lines above the first insulating layer and on the insulating spacers and respectively electrically connected to the plurality of contact plugs.

Abstract translation: 通过使用用于形成接触孔的蚀刻掩模图案，半导体器件和制造半导体器件的方法保持接触插塞和形成在接触插塞上的布线之间的绝缘距离。 所述装置包括包括多个导电区域的基板; 所述基板上的层间绝缘层具有多个所述导电区域露出的接触孔; 覆盖所述层间绝缘层的顶表面的第一绝缘层; 分别通过所述多个接触孔连接到所述多个导电区域的多个接触插塞，所述多个接触插塞具有从所述基板的每个顶部表面到所述基板的顶表面的距离小于距所述顶表面的距离的顶表面 的层间绝缘层到基板的顶面; 多个环状绝缘垫片，其覆盖层间绝缘层的内侧壁，第一绝缘层的内侧壁和接触插塞的上表面的外缘区域，以便暴露出中间区域 接触插塞在接触孔中; 以及在第一绝缘层上方和绝缘间隔物上的多条布线，并分别电连接到多个接触插塞。