公开(公告)号：US06507530B1

公开(公告)日：2003-01-14

申请号：US09967642

申请日：2001-09-28

Applicant: Michael W. Williams ,  James M. Dodd ,  Lloyd L Pollard, II ,  Nitin B Gupte

Inventor： Michael W. Williams ,  James M. Dodd ,  Lloyd L Pollard, II ,  Nitin B Gupte

IPC: G11C700

CPC classification number: G11C11/4078 ,  G11C7/04

Abstract: A memory system includes a plurality of memory device ranks. A memory controller having a connection with the plurality of memory device ranks is adapted to obtain command information being issued to one of the plurality of memory device ranks. The memory controller is also adapted to generate a power weight value based on a command type from the command information. The memory controller increments a power count of the one of the plurality of memory device ranks by the power weight value generated. The memory controller then compares the power count of the one of the plurality of memory device ranks to a threshold value set for the one of the plurality of memory device ranks. If it is determined that the power count exceeds the threshold value, the memory controller is adapted to throttle the one of the plurality of memory device ranks.

Abstract translation: 存储器系统包括多个存储器件等级。 具有与多个存储器装置等级的连接的存储器控​​制器适于获得被发布到多个存储器件等级之一的命令信息。 存储器控制器还适于基于来自命令信息的命令类型来生成功率权重值。 存储器控制器通过生成的功率权重值来增加多个存储器件等级中的一个的功率计数。 存储器控制器然后将多个存储器件等级中的一个的功率计数与为多个存储器件等级中的一个设置的阈值进行比较。 如果确定功率计数超过阈值，则存储器控制器适于调节多个存储器件等级中的一个。

公开(公告)号：US06449213B1

公开(公告)日：2002-09-10

申请号：US09664192

申请日：2000-09-18

Applicant: James M. Dodd ,  Michael W. Williams ,  John B. Halbert ,  Randy M. Bonella

Inventor： James M. Dodd ,  Michael W. Williams ,  John B. Halbert ,  Randy M. Bonella

IPC: G11C800

CPC classification number: G11C7/109 ,  G11C5/063 ,  G11C7/1087 ,  G11C8/00 ,  G11C8/06

Abstract: A memory interface scheme reduces propagation delay by utilizing source-synchronous signaling to transmit address/command information to memory devices. A memory module in accordance with the present invention may include an address/command buffer that samples address/command information responsive to an address/command strobe signal and then passes the address/command information to a memory device on the module. A retiming circuit may be used to control the timing of read-return data from a memory device on the module.

Abstract translation: 存储器接口方案通过利用源同步信令将地址/命令信息发送到存储器件来减少传播延迟。 根据本发明的存储器模块可以包括地址/命令缓冲器，其响应于地址/命令选通信号对地址/命令信息进行采样，然后将地址/命令信息传递到模块上的存储器件。 可以使用重新定时电路来控制来自模块上的存储器件的读取数据的定时。

公开(公告)号：US07024518B2

公开(公告)日：2006-04-04

申请号：US10100312

申请日：2002-03-13

Applicant: John B. Halbert ,  James M. Dodd ,  Chung Lam ,  Randy M. Bonella ,  Thomas J. Holman

Inventor： John B. Halbert ,  James M. Dodd ,  Chung Lam ,  Randy M. Bonella ,  Thomas J. Holman

IPC: G06F12/00

CPC classification number: G11C7/1051 ,  G06F13/1689 ,  G06F13/1694 ,  G11C5/00 ,  G11C5/025 ,  G11C7/1012 ,  G11C7/1066 ,  G11C2207/108

Abstract: Methods and apparatus for a memory system using a new memory module architecture are disclosed. In one embodiment, the memory module has two ranks of memory devices, each rank connected to a corresponding one of two 64-bit-wide data registers. The data registers connect to two 64-bit-wide ports of a 128:64 multiplexer/demultiplexer, and a 64-bit-wide data buffer connects to the opposite port of the multiplexer/demultiplexer. A controller synchronizes the operation of the data registers, the multiplexer/demultiplexer, and the data buffer.In an operating environment, the data buffer connects to a memory bus. When a data access is performed, both ranks exchange data signaling with their corresponding data registers during a single data access. At the buffer, the memory bus data transfer occurs in two consecutive clock cycles, one cycle for each rank. This allows the memory bus transfer rate to double for the same memory bus width and memory device speed.

公开(公告)号：US07000133B2

公开(公告)日：2006-02-14

申请号：US10104676

申请日：2002-03-22

Applicant: James M. Dodd ,  Narendra Khandekar

Inventor： James M. Dodd ,  Narendra Khandekar

IPC: G06F1/26

CPC classification number: G06F1/3225

Abstract: A method of controlling power states in a memory device includes determining if a power-down command is received. A first lower power state is entered if the power-down command is received and the memory device is in a first state. A second lower power state is entered if the power-down command is received and if the memory device is in a second state. The second lower power state is lower than the first lower power state. The memory device remains in a normal operation power state if the power-down command is not received.

Abstract translation: 控制存储器件中的电源状态的方法包括确定是否接收掉电命令。 如果接收到掉电命令并且存储器件处于第一状态，则输入第一低功率状态。 如果接收到掉电命令并且存储器件处于第二状态，则输入第二个较低功率状态。 第二低功率状态低于第一低功率状态。 如果没有接收到掉电命令，则存储器件保持在正常工作状态。

公开(公告)号：US06952745B1

公开(公告)日：2005-10-04

申请号：US10877387

申请日：2004-06-25

Applicant: James M. Dodd ,  Brian P. Johnson ,  Jay C. Wells ,  John B. Halbert

Inventor： James M. Dodd ,  Brian P. Johnson ,  Jay C. Wells ,  John B. Halbert

IPC: G06F13/16 ,  G11C7/10 ,  G06F13/28 ,  G06F3/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/14

CPC classification number: G06F13/1668 ,  G11C7/1027 ,  G11C7/1066 ,  G11C7/1072

Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.

Abstract translation: 本发明包括一种用于控制在存储器件上执行的读和写操作的数据长度的方法和装置。 该方法包括确定可操作地耦合到存储器件的存储器控​​制器可用的第一数量的通道; 确定填充频道的数量的第二数字代表; 基于第一和第二数字计算突发长度; 并且对存储器控制器进行编程以使用突发长度作为在存储器件上执行的读和写操作的数据长度。

公开(公告)号：US06795899B2

公开(公告)日：2004-09-21

申请号：US10104270

申请日：2002-03-22

Applicant: James M. Dodd ,  Howard S. David

Inventor： James M. Dodd ,  Howard S. David

IPC: G06F1200

CPC classification number: G06F13/28

Abstract: In some embodiments, the invention includes a system having a memory controller, a bus, and first and second memory devices. The memory controller requests read and write operations and operates with a burst length. The first and second memory devices are coupled to the memory controller through the bus, the first and second memory devices each having a prefetch length that is greater than the burst length, but performing the requested read and write operations with the burst length. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，本发明包括具有存储器控制器，总线以及第一和第二存储器件的系统。 存储器控制器请求读写操作并以突发长度进行操作。 第一和第二存储器件通过总线耦合到存储器控制器，第一和第二存储器件各自具有大于突发长度的预取长度，但是以突发长度执行所请求的读取和写入操作。 描述和要求保护其他实施例。

公开(公告)号：US06535956B1

公开(公告)日：2003-03-18

申请号：US09198130

申请日：1998-11-23

Applicant: James M. Dodd ,  Brian K. Langendorf

Inventor： James M. Dodd ,  Brian K. Langendorf

IPC: G06F1200

CPC classification number: G06F12/0802

Abstract: A mechanism for automatically detecting whether a selected type of cache memory is implemented within a cache memory element. The mechanism features a dedicated control line coupled between the cache memory element and a system controller. Logic circuitry is coupled to the control line to force the line to a first logic level in the event that the cache memory element has no connection to support the control line. However, if the cache memory element contains the selected type of cache memory, the logic circuitry is unable to for force the control line to go from a second logic level to the first logic level. After system reset, the system controller samples the voltage on the control line to determine whether the cache memory element is implemented with the selected type of cache memory.

Abstract translation: 用于自动检测在高速缓冲存储器元件内是否实现所选类型的高速缓冲存储器的机构。 该机制具有耦合在高速缓冲存储器元件和系统控制器之间的专用控制线。 在高速缓冲存储器元件没有连接以支持控制线的情况下，逻辑电路耦合到控制线以强制线路进入第一逻辑电平。 然而，如果高速缓冲存储器元件包含所选择的高速缓冲存储器类型，则逻辑电路不能强制控制线从第二逻辑电平转到第一逻辑电平。 系统复位后，系统控制器对控制线上的电压进行采样，以确定高速缓存存储器元件是否使用选定类型的高速缓冲存储器实现。

公开(公告)号：US5898856A

公开(公告)日：1999-04-27

申请号：US528699

申请日：1995-09-15

Applicant: James M. Dodd ,  Brian K. Langendorf

Inventor： James M. Dodd ,  Brian K. Langendorf

IPC: G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC classification number: G06F12/0802

Abstract: A mechanism for automatically detecting whether a selected type of cache memory is implemented within a cache memory element. The mechanism features a dedicated control line coupled between the cache memory element and a system controller. Logic circuitry is coupled to the control line to force the line to a first logic level in the event that the cache memory element has no connection to support the control line. However, if the cache memory element contains the selected type of cache memory, the logic circuitry is unable to for force the control line to go from a second logic level to the first logic level. After system reset, the system controller samples the voltage on the control line to determine whether the cache memory element is implemented with the selected type of cache memory.

Abstract translation: 用于自动检测在高速缓冲存储器元件内是否实现所选类型的高速缓冲存储器的机构。 该机制具有耦合在高速缓冲存储器元件和系统控制器之间的专用控制线。 在高速缓冲存储器元件没有连接以支持控制线的情况下，逻辑电路耦合到控制线以强制线路进入第一逻辑电平。 然而，如果高速缓冲存储器元件包含所选择的高速缓冲存储器类型，则逻辑电路不能强制控制线从第二逻辑电平转到第一逻辑电平。 系统复位后，系统控制器对控制线上的电压进行采样，以确定高速缓存存储器元件是否使用选定类型的高速缓冲存储器实现。

公开(公告)号：US06934823B2

公开(公告)日：2005-08-23

申请号：US09821421

申请日：2001-03-29

Applicant: Michael W Williams ,  James M Dodd

Inventor： Michael W Williams ,  James M Dodd

IPC: G06F13/16 ,  G06F12/06

CPC classification number: G06F13/1605 ,  G06F13/1689

Abstract: A method of handling memory read return data from different time domains includes determining a number of distinct memory device ranks. A time domain for each of the distinct memory device ranks is determined. A transaction is scheduled based on the time domain for each of the distinct memory device ranks so that at least one of data collisions and out-of-order data returns are prevented.

Abstract translation: 一种处理来自不同时域的存储器读取返回数据的方法包括确定不同存储器件级别的数量。 确定每个不同存储器设备等级的时域。 基于每个不同存储器件等级的时域来调度事务，从而防止数据冲突和乱序数据返回中的至少一个返回。

公开(公告)号：US06781911B2

公开(公告)日：2004-08-24

申请号：US10119919

申请日：2002-04-09

Applicant: Robert J. Riesenman ,  James M. Dodd

Inventor： Robert J. Riesenman ,  James M. Dodd

IPC: G11C700

CPC classification number: G11C5/143 ,  G11C7/20 ,  G11C11/4072

Abstract: Methods and devices for a memory system are disclosed. A digital memory device can receive power-down commands during the pendency of an active-mode command such as a burst read or write, that is, “early”. The device shuts down some circuitry, such as address and command registers, immediately upon receipt of the early power-down command. Other device components, e.g., those involved in servicing the burst read or write, remain active at least until their portion of the command has been completed. In some embodiments, the early power-down command can be issued concurrently with an active-mode command as an option to that command, freeing a memory controller from having to schedule and issue power-down commands separately. Significant power savings, as compared to those obtained with prior-art memory device power-down modes, are possible.

Abstract translation: 公开了用于存储器系统的方法和装置。 数字存储设备可以在诸如突发读或写之类的活动模式命令（即“早”）的等待期间接收掉电命令。 该设备在收到早期停电命令后立即关闭某些电路，如地址和命令寄存器。 其他设备组件，例如涉及服务突发读或写操作的设备组件至少直到其命令的部分已经完成为止。 在一些实施例中，早期掉电命令可以与作为该命令的选项的主动模式命令同时发出，释放存储器控制器不必分别调度和发布掉电命令。 与使用现有技术的存储器件掉电模式获得的功率相比，显着的功率节省是可能的。