公开(公告)号：US08560816B2

公开(公告)日：2013-10-15

申请号：US12827842

申请日：2010-06-30

Applicant: Mark S. Moir ,  David Dice ,  Daniel S. Nussbaum ,  James R. Goodman

Inventor： Mark S. Moir ,  David Dice ,  Daniel S. Nussbaum ,  James R. Goodman

IPC: G06F9/00

CPC classification number: G06F9/3863 ,  G06F9/3834 ,  G06F9/3859

Abstract: Systems and methods described herein for performing incremental register checkpointing may employ a special register to indicate which registers have already been checkpointed. This register may include one bit per register. These systems may also include a special pointer register whose value identifies a location in user memory or in dedicated on-chip storage at which a copy of a register's value should be saved by a checkpointing operation. Only registers modified during speculative execution or execution of a transaction may be checkpointed (e.g., when register modifying instructions are encountered) and subsequently restored (e.g., due to misspeculation or transaction abort), rather than all of the registers of the processor. Each register may be checkpointed at most once for a given speculative episode or atomic transaction. Setting a bit in the special register may prevent checkpointing of the corresponding register. Setting all of the bits in the special register may disable checkpointing.

Abstract translation: 本文描述的用于执行增量寄存器检查点的系统和方法可以使用特殊寄存器来指示哪些寄存器已经被检查点。 该寄存器可以包括每个寄存器一位。 这些系统还可以包括特殊的指针寄存器，其特征指针寄存器的值标识用户存储器中的位置或专用片上存储器，通过检查点操作应该保存寄存器值的副本。 只有在推测性执行或执行交易期间修改的寄存器可以是检查点（例如，当遇到寄存器修改指令时）并且随后恢复（例如，由于错误设置或事务中止）而不是处理器的所有寄存器。 对于给定的投机事件或原子事务，每个寄存器最多可以被检查点一次。 在特殊寄存器中设置一位可能会阻止相应寄存器的检查点。 设置特殊寄存器中的所有位可能会禁用检查点。

公开(公告)号：US08140497B2

公开(公告)日：2012-03-20

申请号：US11967381

申请日：2007-12-31

Applicant: James R. Goodman ,  Mark S. Moir ,  Fu'ad W. F. Al Tabba′ ,  Cong Wang

Inventor： James R. Goodman ,  Mark S. Moir ,  Fu'ad W. F. Al Tabba′ ,  Cong Wang

IPC: G06F17/00

CPC classification number: G06F9/467

Abstract: Systems and methods for implementing and using nonblocking zero-indirection software transactional memory (NZSTM) are disclosed. NZSTM systems implement object-based software transactional memory that eliminates all levels of indirection except in the uncommon case of a conflict with an unresponsive thread. Shared data is co-located with a header in an NZObject, and is addressable at a fixed offset from the header. Conflicting transactions are requested to abort themselves without being forced to abort. NZObjects are modified in place when there are no conflicts, and when a conflicting transaction acknowledges the abort request. In the uncommon case, NZObjects are inflated to introduce a locator and some levels of indirection, and are restored to their un-inflated form following resolution of the conflict. In some embodiments, transactions are executed using best effort hardware transactional memory if it is available and effective, and software transactional memory if not, yielding a hybrid transactional memory system, NZTM.

Abstract translation: 公开了用于实现和使用非阻塞零间接软件事务存储器（NZSTM）的系统和方法。 NZSTM系统实现了基于对象的软件事务内存，消除了所有级别的间接，除非是与无响应线程冲突的罕见情况。 共享数据与NZObject中的头部位于一起，并且可以与头部固定的偏移量进行寻址。 要求冲突交易中止自己而不被迫中止。 当没有冲突时，NZObjects被修改就位，当冲突的事务确认中止请求时。 在不常见的情况下，NZObjects被膨胀以引入定位器和一定程度的间接性，并且在解决冲突之后恢复到它们没有膨胀的形式。 在一些实施例中，如果可用且有效，则使用尽力而为的硬件事务存储器来执行事务，如果不是，则使用软件事务存储器，产生混合事务存储器系统NZTM。

公开(公告)号：US20120005461A1

公开(公告)日：2012-01-05

申请号：US12827842

申请日：2010-06-30

Applicant: Mark S. Moir ,  David Dice ,  Daniel S. Nussbaum ,  James R. Goodman

Inventor： Mark S. Moir ,  David Dice ,  Daniel S. Nussbaum ,  James R. Goodman

IPC: G06F9/312

CPC classification number: G06F9/3863 ,  G06F9/3834 ,  G06F9/3859

Abstract: Systems and methods described herein for performing incremental register checkpointing may employ a special register to indicate which registers have already been checkpointed. This register may include one bit per register. These systems may also include a special pointer register whose value identifies a location in user memory or in dedicated on-chip storage at which a copy of a register's value should be saved by a checkpointing operation. Only registers modified during speculative execution or execution of a transaction may be checkpointed (e.g., when register modifying instructions are encountered) and subsequently restored (e.g., due to misspeculation or transaction abort), rather than all of the registers of the processor. Each register may be checkpointed at most once for a given speculative episode or atomic transaction. Setting a bit in the special register may prevent checkpointing of the corresponding register. Setting all of the bits in the special register may disable checkpointing.

Abstract translation: 本文描述的用于执行增量寄存器检查点的系统和方法可以使用特殊寄存器来指示哪些寄存器已经被检查点。 该寄存器可以包括每个寄存器一位。 这些系统还可以包括特殊的指针寄存器，其特征指针寄存器的值标识用户存储器中的位置或专用片上存储器，通过检查点操作应该保存寄存器值的副本。 只有在推测性执行或执行交易期间修改的寄存器可以是检查点（例如，当遇到寄存器修改指令时）并且随后恢复（例如，由于错误设置或事务中止）而不是处理器的所有寄存器。 对于给定的投机事件或原子事务，每个寄存器最多可以被检查点一次。 在特殊寄存器中设置一位可能会阻止相应寄存器的检查点。 设置特殊寄存器中的所有位可能会禁用检查点。

公开(公告)号：US20110225375A1

公开(公告)日：2011-09-15

申请号：US13113432

申请日：2011-05-23

Applicant: Ravi Rajwar ,  James R. Goodman

Inventor： Ravi Rajwar ,  James R. Goodman

IPC: G06F12/00

CPC classification number: G06F9/528 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/52 ,  G06F12/0808 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/128 ,  G06F12/1458 ,  G06F12/1475 ,  G06F2212/1041 ,  G06F2212/1052 ,  G06F2212/283 ,  G06F2212/62

Abstract: One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.

Abstract translation: 本发明的一个实施例提供一种通过推测性地执行代码的关键部分来有助于避免锁定的系统。 在操作期间，系统允许进程在程序中推测性地执行代码的关键部分而不首先获得与关键部分相关联的锁定。 如果该过程随后完成关键部分而没有遇到来自另一进程的干扰数据访问，则系统进行在推测执行期间所做的更改，并且通过关键部分恢复程序的正常非推测性执行。 否则，如果在执行关键部分期间遇到来自其他进程的干扰数据访问，则系统将丢弃在推测执行期间所做的更改，并尝试重新执行临界部分。

公开(公告)号：US07962699B2

公开(公告)日：2011-06-14

申请号：US12843828

申请日：2010-07-26

Applicant: Ravi Rajwar ,  James R. Goodman

Inventor： Ravi Rajwar ,  James R. Goodman

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F9/528 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/52 ,  G06F12/0808 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/128 ,  G06F12/1458 ,  G06F12/1475 ,  G06F2212/1041 ,  G06F2212/1052 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/69

Abstract: One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.

Abstract translation: 本发明的一个实施例提供一种通过推测性地执行代码的关键部分来有助于避免锁定的系统。 在操作期间，系统允许进程在程序中推测性地执行代码的关键部分而不首先获得与关键部分相关联的锁定。 如果该过程随后完成关键部分而没有遇到来自另一进程的干扰数据访问，则系统进行在推测执行期间所做的更改，并且通过关键部分恢复程序的正常非推测性执行。 否则，如果在执行关键部分期间遇到来自其他进程的干扰数据访问，则系统将丢弃在推测执行期间所做的更改，并尝试重新执行临界部分。

公开(公告)号：US07917646B2

公开(公告)日：2011-03-29

申请号：US10325427

申请日：2002-12-19

Applicant: Herbert H. J. Hum ,  James R. Goodman ,  Robert H. Beers ,  Rajnish Ghughal

Inventor： Herbert H. J. Hum ,  James R. Goodman ,  Robert H. Beers ,  Rajnish Ghughal

IPC: G06F15/16

CPC classification number: G06F12/0831 ,  G06F12/0826 ,  G06F2212/622

Abstract: A conflict resolution technique provides consistency such that all conflicts can be detected by at least one of the conflicting requestors if each node monitors all requests after that node has made its own request. If a line is in the Exclusive, Modified or Forward state, conflicts are resolved at the node holding the unique copy. The winner of the conflict resolution, and possibly the losers, report the conflict to the home node, which pairs conflict reports and issues forwarding instructions to assure that all requesting nodes eventually receive the requested data. If a requested cache line is either uncached or present only in the Shared state, the home node provides a copy of the cache node and resolves conflicts. In one embodiment, a blackout period after all responses until an acknowledgement message has been received allows all conflicting nodes to be aware of conflicts in which they are involved.

Abstract translation: 冲突解决技术提供一致性，使得如果每个节点在该节点已经做出其自己的请求之后监视所有请求，则冲突请求者中的至少一个可以检测所有冲突。 如果一行处于“独占”，“修改”或“转发”状态，则在保存唯一副本的节点处解决冲突。 冲突解决的胜利者以及可能的失败者将冲突报告给家庭节点，该家庭节点对冲突报告和发出转发指令，以确保所有请求节点最终都接收到所请求的数据。 如果所请求的高速缓存行未被缓存或仅在共享状态下存在，则家庭节点提供缓存节点的副本并解决冲突。 在一个实施例中，在接收到确认消息之后的所有响应之后的停电时段允许所有冲突节点都知道它们涉及的冲突。

公开(公告)号：US07793052B2

公开(公告)日：2010-09-07

申请号：US11967358

申请日：2007-12-31

Applicant: James R. Goodman ,  Mark S. Moir ,  Fu'ad W. F. Al Tabba′ ,  Cong Wang

Inventor： James R. Goodman ,  Mark S. Moir ,  Fu'ad W. F. Al Tabba′ ,  Cong Wang

IPC: G06F12/00

CPC classification number: G06F9/526 ,  G06F9/466 ,  G06F11/141 ,  G06F11/1479 ,  G06F2209/521

Abstract: A hybrid Single-Compare-Single-Store (SCSS) operation may exploit best-effort hardware transactional memory (HTM) for good performance in the case that it succeeds, and may transparently resort to software-mediated transactions if the hardware transactional mechanisms fail. The SCSS operation may compare a value in a control location to a specified expected value, and if they match, may store a new value in a separate data location. The control value may include a global lock, a transaction status indicator, and/or a portion of an ownership record, in different embodiments. If another transaction in progress owns the data location, the SCSS operation may abort the other transaction or may help it complete by copying the other transactions' write set into its own right set before acquiring ownership. A hybrid SCSS operation, which is usually nonblocking, may be applied to building software transactional memories (STMs) and/or hybrid transactional memories (HyTMs), in some embodiments.

Abstract translation: 混合单一比较单存储（SCSS）操作可以在成功的情况下利用尽力而为的硬件事务存储器（HTM）以获得良好的性能，并且如果硬件事务机制失败，则可以透明地诉诸软件介入的事务。 SCSS操作可以将控制位置中的值与指定的预期值进行比较，如果匹配，则可将新值存储在单独的数据位置。 在不同的实施例中，控制值可以包括全局锁定，事务状态指示符和/或所有权记录的一部分。 如果正在进行的另一个交易拥有数据位置，SCSS操作可能会中止其他交易，或者可以在获得所有权之前将其他交易的写入集合复制到自己的权利集中来帮助完成该交易。 在一些实施例中，通常不阻塞的混合SCSS操作可以应用于构建软件事务存储器（STM）和/或混合事务存储器（HyTM）。

公开(公告)号：US07457924B2

公开(公告)日：2008-11-25

申请号：US11482673

申请日：2006-07-06

Applicant: Herbert H. J. Hum ,  James R. Goodman

Inventor： Herbert H. J. Hum ,  James R. Goodman

IPC: G06F12/00

CPC classification number: G06F12/0817 ,  G06F12/0813

Abstract: Use of an import cache and/or an export directory with an agent within to respond to requests for data. The import cache stores data that has been imported through the agent. The export directory stores information related to data that has been exported through the agent. Because the import cache and the export directory only store data that has passed through the agent, not all data transferred within a system are tracked by a single import cache or export directory.

Abstract translation: 使用导入缓存和/或导出目录与其中的代理来响应数据请求。 导入缓存存储通过代理程序导入的数据。 导出目录存储与通过代理导出的数据相关的信息。 因为导入缓存和导出目录只存储已经通过代理的数据，所以并不是系统中传输的所有数据都被单个导入缓存或导出目录跟踪。

公开(公告)号：US07269698B2

公开(公告)日：2007-09-11

申请号：US11069848

申请日：2005-02-28

Applicant: Herbert H. J. Hum ,  James R. Goodman

Inventor： Herbert H. J. Hum ,  James R. Goodman

IPC: G06F13/14

CPC classification number: G06F12/0813 ,  G06F12/0815 ,  G06F2212/2542

Abstract: The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can directly communicate with some number of other nodes in the system. In one embodiment, for each cache line, the address of the cache line is used to designate a node as the “home” node and all other nodes as “peer” nodes. The protocol specifies one set of messages for communication with the line's home node and another set of messages for communication with the line's peer nodes.

Abstract translation: 本文描述的高速缓存一致性协议可用于维护系统的虚拟模型，其中虚拟模型不随系统配置改变而改变。 一般来说，虚拟模型是基于系统中的每个节点可以直接与系统中的其他节点通信的假设。 在一个实施例中，对于每个高速缓存行，高速缓存行的地址用于将节点指定为“家”节点，将所有其他节点指定为“对等”节点。 该协议指定一组消息，用于与线路的家庭节点通信，另一组消息用于与线路的对等节点进行通信。

公开(公告)号：US06954829B2

公开(公告)日：2005-10-11

申请号：US10326232

申请日：2002-12-19

Applicant: Robert H. Beers ,  Herbert H. J. Hum ,  James R. Goodman

Inventor： Robert H. Beers ,  Herbert H. J. Hum ,  James R. Goodman

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0831 ,  G06F12/0813

Abstract: A conflict resolution technique provides consistency such that all conflicts can be detected by at least one of the conflicting requestors if each node monitors all requests after that node has made its own request. If a line is in the Exclusive, Modified or Forward state, conflicts are resolved at the node holding the unique copy. The winner of the conflict resolution, and possibly the losers, report the conflict to the home node, which pairs conflict reports and issues forwarding instructions to assure that all requesting nodes eventually receive the requested data. If a requested cache line is either uncached or present only in the Shared state, the home node provides a copy of the cache node and resolves conflicts. In one embodiment, a blackout period after all responses until an acknowledgement message has been received allows all conflicting nodes to be aware of conflicts in which they are involved.

Abstract translation: 冲突解决技术提供一致性，使得如果每个节点在该节点已经做出其自己的请求之后监视所有请求，则冲突请求者中的至少一个可以检测所有冲突。 如果一行处于“独占”，“修改”或“转发”状态，则在保存唯一副本的节点处解决冲突。 冲突解决的胜利者以及可能的失败者将冲突报告给家庭节点，该家庭节点对冲突报告和发出转发指令，以确保所有请求节点最终都接收到所请求的数据。 如果所请求的高速缓存行未被缓存或仅在共享状态下存在，则家庭节点提供缓存节点的副本并解决冲突。 在一个实施例中，在接收到确认消息之后的所有响应之后的停电时段允许所有冲突节点都知道它们涉及的冲突。