公开(公告)号：US07303952B2

公开(公告)日：2007-12-04

申请号：US10711771

申请日：2004-10-04

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Glenn C. MacDougall ,  Dale W. Martin ,  Kirk D. Peterson ,  Bruce W. Porth

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Glenn C. MacDougall ,  Dale W. Martin ,  Kirk D. Peterson ,  Bruce W. Porth

IPC: H01L21/8238

CPC classification number: H01L21/265 ,  H01L21/28035 ,  H01L21/823842 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of fabricating polysilicon lines and polysilicon gates, the method of including: providing a substrate; forming a dielectric layer on a top surface of the substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species about contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.

Abstract translation: 一种制造多晶硅线路和多晶硅栅极的方法，所述方法包括：提供衬底; 在所述基板的顶表面上形成介电层; 在所述电介质层的顶表面上形成多晶硅层; 用N掺杂物种注入多晶硅层，所述N掺杂物物质包含在所述多晶硅层内; 用含氮物质注入多晶硅层，含氮物质基本上包含在多晶硅层内。

公开(公告)号：US07240322B2

公开(公告)日：2007-07-03

申请号：US10907494

申请日：2005-04-04

Applicant: James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

Inventor： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

IPC: G06F17/50

CPC classification number: H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

Abstract translation: 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状， 集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

公开(公告)号：US07217968B2

公开(公告)日：2007-05-15

申请号：US10905097

申请日：2004-12-15

Applicant: James W. Adkisson ,  John Ellis-Monaghan ,  Mark D. Jaffe ,  Jerome B. Lasky

Inventor： James W. Adkisson ,  John Ellis-Monaghan ,  Mark D. Jaffe ,  Jerome B. Lasky

IPC: H01L31/062

CPC classification number: H01L27/14603 ,  H01L27/14601 ,  H01L27/14689 ,  H01L29/66621

Abstract: A novel image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate, a gate comprising a dielectric layer and gate conductor formed on the dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. Part of the gate conductor bottom is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region.

Abstract translation: 一种新颖的图像传感器单元结构及其制造方法。 成像传感器包括基板，包括电介质层和形成在电介质层上的栅极导体的栅极，形成在与栅极导体的第一侧相邻的基板的表面下面的第一导电类型的收集阱层，钉扎层 在基板表面上形成在集合阱顶部的第二导电类型的第一导电类型的扩散区和在栅极导体的第二侧附近形成的第一导电类型的扩散区，栅极导体在集电阱层和扩散区之间形成沟道区 。 栅极导体底部的一部分凹陷在基板的表面下方。 优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到使得收集阱与沟道区相交的深度。

公开(公告)号：US07112845B2

公开(公告)日：2006-09-26

申请号：US10064171

申请日：2002-06-18

Applicant: James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Jed H. Rankin

Inventor： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Jed H. Rankin

IPC: H01L27/01

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66818

Abstract: A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.

公开(公告)号：US07089514B2

公开(公告)日：2006-08-08

申请号：US10710879

申请日：2004-08-10

Applicant: James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Francis Gravel ,  Leendert M. Huisman ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Kenneth Rowe ,  Thomas G. Sopchak ,  David E. Sweenor

Inventor： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Francis Gravel ,  Leendert M. Huisman ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Kenneth Rowe ,  Thomas G. Sopchak ,  David E. Sweenor

IPC: G06F17/50

CPC classification number: G01R31/31718 ,  G01R31/318342

Abstract: A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.

Abstract translation: 一种半导体芯片缺陷诊断方法。 该方法包括以下步骤：（a）识别电路设计的M个设计结构和N个物理特性，其中M和N是正整数，其中M个设计结构的每个设计结构可以通过或失败，并且其中每个 N物理特性的物理特性存在于M设计结构的至少一个设计结构中; （b）对于电路设计的M设计结构的每个设计结构，确定故障率并确定故障率是高还是低; 和（c）如果存在N个物理特性的物理特性的M设计结构的每个设计结构具有高故障率，则将物理特性标记为可能至少包含缺陷。

公开(公告)号：US07009237B2

公开(公告)日：2006-03-07

申请号：US10709450

申请日：2004-05-06

Applicant: James W. Adkisson ,  Gary B. Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl J. Radens

Inventor： James W. Adkisson ,  Gary B. Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC: H01L27/108

CPC classification number: H01L27/10841 ,  H01L27/10864 ,  H01L27/10867

Abstract: The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.

Abstract translation: 本发明提供了一种形成在绝缘体上硅衬底上的垂直存储器件，其中接触绝缘体上硅衬底的上表面的位线通过上带扩散区域电连接到垂直存储器件 掩埋氧化层。 上带扩散区域通过横向蚀刻掩埋氧化物区域的一部分而形成，其中沉积掺杂多晶硅。 上带区域扩散区域还为垂直存储器件的垂直晶体管提供源极。 垂直存储器件还可以与具有形成在绝缘体上硅衬底上的逻辑器件的支撑区域集成。

公开(公告)号：US06960744B2

公开(公告)日：2005-11-01

申请号：US10604609

申请日：2003-08-04

Applicant: James W. Adkisson ,  Anthony Kendall Stamper

Inventor： James W. Adkisson ,  Anthony Kendall Stamper

IPC: H01C10/00 ,  H01L27/08 ,  H05B1/02

CPC classification number: H01C10/00 ,  H01L27/0802

Abstract: A device having a resistor and a heater disposed proximate to the resistor and capable of raising the temperature of the resistor. The device further includes a dieletric disposed between the heater and the resistor and a tuner electrically coupled to the resistor. The heater adjusts the resistance of the resistor in response to the tuner.

Abstract translation: 一种具有电阻器和靠近电阻器设置并能够提高电阻器温度的加热器的器件。 该装置还包括设置在加热器和电阻器之间的小孔，以及电耦合到电阻器的调谐器。 加热器根据调谐器调节电阻的电阻。

公开(公告)号：US06670255B2

公开(公告)日：2003-12-30

申请号：US09965289

申请日：2001-09-27

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Peter B. Gray ,  Anthony K. Stamper

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Peter B. Gray ,  Anthony K. Stamper

IPC: H01L21331

CPC classification number: H01L27/1203 ,  H01L27/0664

Abstract: Disclosed is a method of fabricating a lateral semiconductor device, comprising: providing a substrate, having at least an upper silicon portion forming at least one first dopant type region and at least one second dopant type region in the upper portion of the substrate, at least one of the first dopant type regions abutting at least one of the second dopant type regions and thereby forming at least one PN junction; and forming at least one protective island on a top surface of the upper silicon portion, the protective island extending the length of the PN junction and overlapping a portion of the first dopant type region and a portion of an abutting second dopant type region.

Abstract translation: 公开了一种制造横向半导体器件的方法，包括：提供衬底，至少具有在衬底的上部中至少形成至少一个第一掺杂剂型区域和至少一个第二掺杂剂类型区域的上硅部分，至少 第一掺杂剂类型区域中的一个与第二掺杂剂类型区域中的至少一个邻接，从而形成至少一个PN结; 以及在所述上硅部分的顶表面上形成至少一个保护岛，所述保护岛延伸所述PN结的长度并与所述第一掺杂剂型区域的一部分和邻接的第二掺杂剂型区域的一部分重叠。

公开(公告)号：US06563131B1

公开(公告)日：2003-05-13

申请号：US09586501

申请日：2000-06-02

Applicant: James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Christopher S. Putnam ,  Jed H. Rankin

Inventor： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Christopher S. Putnam ,  Jed H. Rankin

IPC: H01L2906

CPC classification number: H01L29/78696 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/78654

Abstract: Off-current is not compromised in a field effect transistor having a gate length less than 100 nanometers in length by maintaining the conduction channel width one-half to one-quarter of the gate length and locating the gate on at least two sides of the conduction channel and to thus create a full depletion device. Such a narrow conduction channel is achieved by forming a trough at minimum lithographic dimensions, forming sidewalls within the trough and etching the gate structure self-aligned with the sidewalls. The conduction channel is then epitaxially grown from the source structure in the trough such that the source, conduction channel and drain region are a unitary monocrystalline structure.

Abstract translation: 在栅极长度小于100纳米的场效应晶体管中，通过将导通沟道宽度保持为栅极长度的二分之一至四分之一，并将栅极定位在导电的至少两侧，不会损害截止电流 通道，从而创建一个完全耗尽的设备。 通过在最小光刻尺寸下形成槽，在槽内形成侧壁并蚀刻与侧壁自对准的栅极结构来实现这种窄导电沟道。 然后从槽中的源结构外延生长传导通道，使得源极，导电沟道和漏极区域是单一的单晶结构。

公开(公告)号：US06350653B1

公开(公告)日：2002-02-26

申请号：US09689096

申请日：2000-10-12

Applicant: James W. Adkisson ,  Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Jack A. Mandelman

Inventor： James W. Adkisson ,  Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Jack A. Mandelman

IPC: H01L21336

CPC classification number: H01L27/10864 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator (“SOI”) regions and where buried, doped glass is used as a mask to form deep trenches for storage in the bulk region. The resulting structure is also disclosed.

Abstract translation: 提出了一种半导体器件，其涉及一种形成嵌入式DRAM和逻辑器件的方法，其中DRAM器件以块状形成，单晶半导体区域和逻辑器件形成在绝缘体上硅（“SOI”）区域中， 其中掩埋的掺杂玻璃用作掩模以形成用于存储在本体区域中的深沟槽。 还公开了所得到的结构。