公开(公告)号：US06563131B1

公开(公告)日：2003-05-13

申请号：US09586501

申请日：2000-06-02

申请人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Christopher S. Putnam ,  Jed H. Rankin

发明人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Christopher S. Putnam ,  Jed H. Rankin

IPC分类号： H01L2906

CPC分类号： H01L29/78696 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/78654

摘要： Off-current is not compromised in a field effect transistor having a gate length less than 100 nanometers in length by maintaining the conduction channel width one-half to one-quarter of the gate length and locating the gate on at least two sides of the conduction channel and to thus create a full depletion device. Such a narrow conduction channel is achieved by forming a trough at minimum lithographic dimensions, forming sidewalls within the trough and etching the gate structure self-aligned with the sidewalls. The conduction channel is then epitaxially grown from the source structure in the trough such that the source, conduction channel and drain region are a unitary monocrystalline structure.

摘要翻译： 在栅极长度小于100纳米的场效应晶体管中，通过将导通沟道宽度保持为栅极长度的二分之一至四分之一，并将栅极定位在导电的至少两侧，不会损害截止电流 通道，从而创建一个完全耗尽的设备。 通过在最小光刻尺寸下形成槽，在槽内形成侧壁并蚀刻与侧壁自对准的栅极结构来实现这种窄导电沟道。 然后从槽中的源结构外延生长传导通道，使得源极，导电沟道和漏极区域是单一的单晶结构。

公开(公告)号：US07361556B2

公开(公告)日：2008-04-22

申请号：US11495518

申请日：2006-07-31

申请人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

发明人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

摘要翻译： 通过形成外延生长的通道，随后是镶嵌栅极，制造双栅极绝缘体上硅（SOI）MOSFET。 双门控MOSFET具有窄通道，这增加了每个布局宽度的电流驱动，并提供了低导通电压。

公开(公告)号：US07112845B2

公开(公告)日：2006-09-26

申请号：US10064171

申请日：2002-06-18

申请人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Jed H. Rankin

发明人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Jed H. Rankin

IPC分类号： H01L27/01

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66818

摘要： A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.

公开(公告)号：US06472258B1

公开(公告)日：2002-10-29

申请号：US09711725

申请日：2000-11-13

申请人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Jed H. Rankin

发明人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Jed H. Rankin

IPC分类号： H01L2130

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66818

摘要： A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.

摘要翻译： 场效应晶体管由亚光刻导电沟道和双栅极形成，该双栅极通过简单的工艺由绝缘体上硅晶片开始形成，允许大多数蚀刻工艺使用掩埋氧化物作为蚀刻停止。 通过硅化物侧壁或衬垫实现栅极，源极和漏极的低电阻率，而通过从源极和漏极区域边缘凹陷硅化物和多晶硅双栅极结构来实现低栅极至结电容。

公开(公告)号：US07265417B2

公开(公告)日：2007-09-04

申请号：US10867772

申请日：2004-06-16

申请人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

发明人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L27/01

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

公开(公告)号：US07163864B1

公开(公告)日：2007-01-16

申请号：US09691353

申请日：2000-10-18

申请人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

发明人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

摘要翻译： 通过形成外延生长的通道，随后是镶嵌栅极，制造双栅极绝缘体上硅（SOI）MOSFET。 双门控MOSFET具有窄通道，这增加了每个布局宽度的电流驱动，并提供了低导通电压。

公开(公告)号：US06448590B1

公开(公告)日：2002-09-10

申请号：US09695199

申请日：2000-10-24

申请人： James W. Adkisson ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Jeffrey B. Johnson ,  Erin C. Jones ,  Hon-Sum P. Wong

发明人： James W. Adkisson ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Jeffrey B. Johnson ,  Erin C. Jones ,  Hon-Sum P. Wong

IPC分类号： H01L2710

CPC分类号： H01L29/4916 ,  H01L21/82345 ,  H01L29/4238 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66666 ,  H01L29/7827

摘要： A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.

摘要翻译： 通过提供具有多个阈值电压的晶片来实现用于非常大规模集成电路芯片的较短栅长FET。 通过组合多个功能门极材料来开发多个阈值电压。 栅极材料以预定图案几何对准，使得每个栅极材料与其它栅极材料相邻。 开发了用于多阈值电压设计的图案化线性阵列实施例。 形成多阈值电压FET的方法需要在半导体晶片内的对准沟槽中布置不同的栅极材料，其中每个栅极材料表示单独的功函数。 栅极材料被布置成彼此靠近以适应小栅极长度设计。

公开(公告)号：US07494748B2

公开(公告)日：2009-02-24

申请号：US10904308

申请日：2004-11-03

申请人： James W. Adkisson ,  Eric M. Coker ,  Christopher K. Magg ,  Jed H. Rankin ,  Anthony K. Stamper

发明人： James W. Adkisson ,  Eric M. Coker ,  Christopher K. Magg ,  Jed H. Rankin ,  Anthony K. Stamper

IPC分类号： G03F1/00

CPC分类号： G03F1/72 ,  G03F1/70

摘要： A method for correction of defects in lithography masks includes determining the existence of mask defects on an original mask, and identifying a stitchable zone around each of the mask defects found on the original mask. Each of the identified stitchable zones on the original mask is blocked out such that circuitry within the stitchable zones is not printed out during exposure of the original mask. A repair mask is formed, the repair mask including corrected circuit patterns from each of the identified stitchable zones.

摘要翻译： 用于校正光刻掩模中的缺陷的方法包括确定原始掩模上的掩模缺陷的存在，以及识别在原始掩模上发现的每个掩模缺陷周围的可缝合区域。 原始掩模上的每个识别的可缝合区域被阻挡，使得在原始掩模曝光期间不能打印出可缝合区域内的电路。 形成修复掩模，修复掩模包括来自每个识别的可缝合区域的校正电路图案。

公开(公告)号：US06030541A

公开(公告)日：2000-02-29

申请号：US100542

申请日：1998-06-19

申请人： James W. Adkisson ,  Michael Caterer ,  James T. Marsh ,  Hung Ng ,  James M. Oberschmidt ,  Jed H. Rankin

发明人： James W. Adkisson ,  Michael Caterer ,  James T. Marsh ,  Hung Ng ,  James M. Oberschmidt ,  Jed H. Rankin

IPC分类号： H01L21/027 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/033

CPC分类号： H01L21/0276 ,  H01L21/28123 ,  H01L21/32139

摘要： A pattern in a surface is defined by providing on the surface a hard mask material; depositing an anti-reflective coating on the hard mask material; applying a photoresist layer on the anti-reflective coating; patterning the photoresist layer, anti-reflective layer and hard mask material; and removing the remaining portions of the photoresist layer and anti-reflective layer; and then patterning the substrate using the hard mask as the mask. Also provided is a structure for defining a pattern in a surface which comprises a surface having a hard mask material thereon; an anti-reflective coating located on the hard mask material; and a photoresist located on the anti-reflective coating. Also provided is an etchant composition for removing the hard mask material which comprises an aqueous composition of HF and chlorine.

摘要翻译： 通过在表面上提供硬掩模材料来限定表面中的图案; 在所述硬掩模材料上沉积抗反射涂层; 在抗反射涂层上施加光致抗蚀剂层; 图案化光致抗蚀剂层，抗反射层和硬掩模材料; 并除去光致抗蚀剂层和抗反射层的剩余部分; 然后使用硬掩模作为掩模来图案化衬底。 还提供了一种用于在表面上限定图案的结构，其包括其上具有硬掩模材料的表面; 位于硬掩模材料上的抗反射涂层; 以及位于抗反射涂层上的光致抗蚀剂。 还提供了用于除去硬掩模材料的蚀刻剂组合物，其包含HF和氯的水性组合物。

公开(公告)号：US06445194B1

公开(公告)日：2002-09-03

申请号：US09788084

申请日：2001-02-16

申请人： James W. Adkisson ,  Arne W. Ballantine ,  Ralph W. Young

发明人： James W. Adkisson ,  Arne W. Ballantine ,  Ralph W. Young

IPC分类号： G01R2726

CPC分类号： H01L22/34 ,  G11C2029/0403 ,  H01L21/31612

摘要： The invention provides a monitor wafer and a method using the wafer to measure the conformality of dielectric films and in particular, for measuring the sidewall deposition thickness of dielectric films.

摘要翻译： 本发明提供一种监测晶片和使用晶片来测量介电膜的共形性的方法，特别是用于测量电介质膜的侧壁沉积厚度。