公开(公告)号：US5625522A

公开(公告)日：1997-04-29

申请号：US297629

申请日：1994-08-29

申请人： Jeffrey T. Watt

发明人： Jeffrey T. Watt

IPC分类号： H01L27/02 ,  H02H3/22

CPC分类号： H01L27/0251

摘要： A protective circuit for protecting internal circuits of semiconductor integrated circuits (ICs) from ElectroStatic Discharges (ESD) into a voltage conduit of a semiconductor IC. The protective circuit is coupled in parallel with the internal circuit of the semiconductor IC such that the protective circuit and the internal circuit are each coupled to a first voltage conduit at a first reference voltage at one end and to a second voltage conduit at a second reference voltage at another end. The protective circuit includes an ESD protection device (or devices) for channeling an ESD discharge from the first voltage conduit through the protective circuit to the second voltage conduit. The protective circuit also includes a control circuit for turning "on" (e.g. operating in a low impedance state) the ESD protection device during the occurrence of the ESD discharge into the first voltage conduit. Furthermore, the control circuit turns "on" the ESD protection device before other devices in the internal circuit are damaged as a result of the ESD discharge. Therefore, by channeling the ESD discharge through the ESD protection circuit when an ESD discharge is recognized, but before other devices in the internal circuit are damaged, the ESD protection circuit prevents the internal circuit from being damaged during an ESD discharge.

摘要翻译： 一种保护电路，用于将半导体集成电路（IC）的内部电路从静电放电（ESD）保护到半导体IC的电压导管中。 保护电路与半导体IC的内部电路并联耦合，使得保护电路和内部电路各自以一端的第一参考电压和第二参考电压的第二电压导管耦合到第一电压导管 另一端的电压。 保护电路包括用于将来自第一电压导管的ESD放电通过保护电路引导到第二电压导管的ESD保护装置（或装置）。 保护电路还包括用于在ESD放电进入第一电压导管期间使ESD保护装置“接通”（例如，以低阻抗状态工作）的控制电路。 此外，由于ESD放电，控制电路在内部电路中的其他器件损坏之前，使ESD保护器件“导通”。 因此，当识别到ESD放电时，通过ESD保护电路引导ESD放电，但在内部电路中的其他器件损坏之前，ESD保护电路可防止内部电路在ESD放电期间被损坏。

公开(公告)号：US09627138B1

公开(公告)日：2017-04-18

申请号：US13350679

申请日：2012-01-13

申请人： Shuxian Chen ,  Albert Ratnakumar ,  Yan Cui ,  Jeffrey T. Watt

发明人： Shuxian Chen ,  Albert Ratnakumar ,  Yan Cui ,  Jeffrey T. Watt

IPC分类号： H01G4/005 ,  H01G4/30 ,  H01G4/232

CPC分类号： H01G4/30 ,  H01G4/005 ,  H01G4/232

摘要： Apparatus for integrated capacitors and associated methods are disclosed. In one embodiment, an integrated capacitor includes a first plurality of metal members that are fabricated using a first plurality of metal layers, and are oriented in a first orientation. The integrated capacitor also includes a second plurality of metal members that are fabricated using a second plurality of metal layers. The second plurality of metal members are oriented transverse to the first orientation. The integrated capacitor further includes a third plurality of metal members, which are fabricated using a third plurality of metal layers, and are oriented in the first orientation.

公开(公告)号：US09131604B1

公开(公告)日：2015-09-08

申请号：US13078701

申请日：2011-04-01

申请人： Jeffrey T. Watt ,  Shuxian Chen

发明人： Jeffrey T. Watt ,  Shuxian Chen

IPC分类号： H05K1/02

CPC分类号： H05K1/0245 ,  H05K1/0298 ,  H05K2201/097

摘要： A communications path may be formed from intertwined conductive paths. The intertwined conductive paths may be formed from one or more layers of conductive material in the dielectric stack of an integrated circuit. The dielectric stack may include metal layers, via layers, and a pad layer. The conductive paths may be formed from patterned conductive structures in the metal and pad layers. Vias in the via layers may be used to connect metal structures from multiple dielectric stack layers. The communications path may have segments in which the conductive paths run parallel to each other and may have cross-over regions in which the conductive paths cross one another without electrically connecting so that the paths twist about each other along their lengths. The communications path may be used to form a differential transmission line pair that distributes signals such as two-phase clock signals.

摘要翻译： 通信路径可以由缠结的导电路径形成。 相互缠绕的导电路径可以由集成电路的电介质堆叠中的一层或多层导电材料形成。 电介质堆叠可以包括金属层，通孔层和衬垫层。 导电路径可以由金属和衬垫层中的图案化导电结构形成。 通孔层中的通孔可用于连接来自多个电介质堆叠层的金属结构。 通信路径可以具有其中导电路径彼此平行延伸的段，并且可以具有交叉区域，其中导电路径彼此交叉而不进行电连接，使得路径沿其长度彼此相互扭曲。 通信路径可以用于形成分配诸如两相时钟信号的信号的差分传输线对。

公开(公告)号：US20130043536A1

公开(公告)日：2013-02-21

申请号：US13214102

申请日：2011-08-19

申请人： Irfan RAHIM ,  Jeffrey T. WATT ,  Yanzhong XU ,  Lin-Shih LIU

发明人： Irfan RAHIM ,  Jeffrey T. WATT ,  Yanzhong XU ,  Lin-Shih LIU

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L29/7851 ,  H01L21/761 ,  H01L29/66795

摘要： One embodiment relates to a buffered transistor device. The device includes a buffered vertical fin-shaped structure formed in a semiconductor substrate. The vertical fin-shaped structure includes at least an upper semiconductor layer, a buffer region, and at least part of a well region. The buffer region has a first doping polarity, and the well region has a second doping polarity which is opposite to the first doping polarity. At least one p-n junction that at least partially covers a horizontal cross section of the vertical fin-shaped structure is formed between the buffer and well regions. Other embodiments, aspects, and features are also disclosed.

摘要翻译： 一个实施例涉及缓冲晶体管器件。 该器件包括形成在半导体衬底中的缓冲的垂直鳍状结构。 垂直鳍状结构至少包括上半导体层，缓冲区和阱区​​的至少一部分。 缓冲区具有第一掺杂极性，并且阱区具有与第一掺杂极性相反的第二掺杂极性。 在缓冲区和阱区​​之间形成至少部分覆盖垂直鳍状结构的水平横截面的至少一个p-n结。 还公开了其它实施例，方面和特征。

公开(公告)号：US08120112B1

公开(公告)日：2012-02-21

申请号：US11904706

申请日：2007-09-28

申请人： Jeffrey T. Watt ,  Antonio Gallerano

发明人： Jeffrey T. Watt ,  Antonio Gallerano

IPC分类号： H01L23/58

CPC分类号： H01L27/0277

摘要： An electrostatic discharge (ESD) protection circuit includes a first array of transistors, having source and drain doped with a first type of material, arranged in parallel in a first block, and a second array of transistors, having source and drain doped with the first type of material, arranged in parallel in a second block. The ESD protection circuit also includes an active region between the first and second array of transistors doped with a second type of material that is complementary to the first type of material.

摘要翻译： 静电放电（ESD）保护电路包括：第一晶体管阵列，其具有掺杂有第一类型材料的源极和漏极，并排布置在第一块中;以及第二晶体管阵列，其具有源极和漏极掺杂有第一 材料类型，平行布置在第二块中。 ESD保护电路还包括掺杂有与第一类型材料互补的第二类型材料的第一和第二晶体阵列之间的有源区。

公开(公告)号：US08105885B1

公开(公告)日：2012-01-31

申请号：US12852422

申请日：2010-08-06

申请人： Andy L. Lee ,  Jeffrey T. Watt

发明人： Andy L. Lee ,  Jeffrey T. Watt

IPC分类号： H01L21/82

CPC分类号： H03K19/173 ,  G11C5/005 ,  H01L27/0207 ,  H03K19/1736 ,  H03K19/17784

摘要： Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.

摘要翻译： 硬化可编程逻辑器件提供有可编程电路。 可编程电路可以是硬连线的，以实现定制逻辑电路。 可以使用通用制造掩模来形成可编程电路，并且可以用于制造硬化的可编程逻辑器件的产品系列，每一个可以实现不同的定制逻辑电路。 可以使用定制制造掩模来硬编程电路来实现特定的定制逻辑电路。 可编程电路可以是硬连线的，使得实现定制逻辑电路的硬化可编程逻辑器件的信号定时特性可以匹配使用配置数据实现相同定制逻辑电路的可编程逻辑器件的信号定时特性。

公开(公告)号：US20110204493A1

公开(公告)日：2011-08-25

申请号：US12709289

申请日：2010-02-19

申请人： Shuxian Chen ,  Jeffrey T. Watt

发明人： Shuxian Chen ,  Jeffrey T. Watt

IPC分类号： H01L23/52

CPC分类号： H01L29/92 ,  H01L23/5225 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/00

摘要： A shielding structure comprises first and second comb-like structures defined in a first metallization layer on an integrated circuit, each comb-like structure comprising a plurality of teeth, the teeth of each comb-like structure extending toward the other comb-like structure; a first plurality of electrically conducting vias extending upward from the first comb-like structure; a second plurality of electrically conducting vias extending upward from the second comb-like structure; first and second planar structures in a second metallization layer above the first metallization layer; a third plurality of electrically conducting vias extending downward from the first planar structure toward the first plurality of electrically conducting vias; and a fourth plurality of electrically conducting vias extending downward from the second planar structure toward the second plurality of electrically conducting vias. The first and second comb-like structures, the first and second planar structures and the first, second, third, and fourth electrically conducting vias all being at substantially the same potential, preferably ground. In one embodiment, one or more signal lines are located in the second metallization layer between the first and second planar structures; and in another embodiment they are located in a third metallization layer between the first and second metallization layers.

公开(公告)号：US07900164B1

公开(公告)日：2011-03-01

申请号：US10759400

申请日：2004-01-16

申请人： Shuxian Chen ,  Jeffrey T. Watt

发明人： Shuxian Chen ,  Jeffrey T. Watt

IPC分类号： G06F17/50

CPC分类号： G01R27/205 ,  G01R31/046 ,  H01L22/34

摘要： A structure for measuring both interconnect resistance and capacitance. The structure comprises a plurality of metallic interconnects, a first circuit for measuring capacitance charging current at a first interconnect and a second circuit for measuring the voltage drop between two positions at a second interconnect. The first circuit includes two electrically connected pseudo-inverters. Two control signals are fed into the two pseudo-inverters such that their associated capacitances are charged and discharged periodically. The first interconnect capacitance is determined by measuring the difference of charging currents between the two pseudo-inverters. A constant current flows through the second circuit and the interconnect resistance is determined by the voltage drop and the constant current.

摘要翻译： 用于测量互连电阻和电容两者的结构。 该结构包括多个金属互连，用于测量第一互连处的电容充电电流的第一电路和用于测量在第二互连处的两个位置之间的电压降的第二电路。 第一电路包括两个电连接的伪逆变器。 两个控制信号被馈送到两个伪反相器中，使得其相关联的电容被周期性地充电和放电。 通过测量两个伪逆变器之间的充电电流的差异来确定第一互连电容。 恒定电流流过第二电路，并且互连电阻由电压降和恒定电流决定。

公开(公告)号：US07881041B1

公开(公告)日：2011-02-01

申请号：US12858183

申请日：2010-08-17

申请人： Shuxian Chen ,  Jeffrey T. Watt

发明人： Shuxian Chen ,  Jeffrey T. Watt

IPC分类号： H01G4/228

CPC分类号： H01G4/38 ,  H01G4/005 ,  H01G4/01 ,  H01G4/228 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-segment capacitor fabricated on a semiconductor substrate includes M×N capacitor segments arranged in a matrix of M rows and N columns. Each capacitor segment includes two groups of conductive fingers preferably made of metal wires. The metal wire fingers are distributed within multiple metal layers in such a manner that two neighboring parallel metal wire fingers within a particular metal layer are electrically insulated and connected to different terminals of the capacitor. Further, at least the longitudinal axes of the parallel metal wire fingers within two different metal layers are not parallel to each other within the same capacitor segment.

摘要翻译： 制造在半导体衬底上的多段电容器包括以M行和N列为矩阵排列的M×N个电容器段。 每个电容器段包括优选由金属线制成的两组导电指状物。 金属线指以这样的方式分布在多个金属层内，使得特定金属层内的两个相邻的平行金属线指电绝缘并连接到电容器的不同端子。 此外，至少两个不同金属层内的平行金属线指的纵向轴线在相同的电容器段内彼此不平行。

公开(公告)号：US07859804B1

公开(公告)日：2010-12-28

申请号：US11836705

申请日：2007-08-09

申请人： Antonio Gallerano ,  Jeffrey T. Watt

发明人： Antonio Gallerano ,  Jeffrey T. Watt

IPC分类号： H02H9/00

CPC分类号： H01L27/0262

摘要： This relates to a sense circuit to detect an ESD event and turn on an SCR to discharge the ESD event. In a preferred embodiment, the circuit comprises a resistor in the signal path to/from an I/O buffer, a sense circuit in parallel with the resistor, an SCR connected between ground and a node between the resistor and the I/O pad, and an I/O buffer connected between ground and the other end of the resistor. When the sense circuit detects a significant voltage drop across the resistor, it injects current into the SCR, thereby turning on the SCR and discharging the ESD event.

摘要翻译： 这涉及检测ESD事件并接通SCR以放电ESD事件的感测电路。 在优选实施例中，该电路包括到I / O缓冲器的信号路径中的电阻器，与该电阻器并联的感测电路，连接在地之间的SCR与电阻器和I / O焊盘之间的节点， 以及连接在电阻器的地和另一端之间的I / O缓冲器。 当感测电路检测到电阻两端的显着电压降时，它将电流注入到SCR中，从而导通SCR并释放ESD事件。