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    PROJECTOR AND MULTIPLE PROJECTION CONTROL METHOD OF THE PROJECTOR
    22.
    发明申请
    PROJECTOR AND MULTIPLE PROJECTION CONTROL METHOD OF THE PROJECTOR 有权
    投影机投影机和投影机多项投影控制方法

    公开(公告)号：US20090085828A1

    公开(公告)日：2009-04-02

    申请号：US12032711

    申请日：2008-02-18

    Applicant: Gene Moo LEE ,  Jin Wook Lee ,  Hun Lim

    Inventor： Gene Moo LEE ,  Jin Wook Lee ,  Hun Lim

    IPC: G09G5/00

    CPC classification number: H04N9/3194 ,  G06F3/0488 ,  G06F3/1423 ,  G09G5/14 ,  H04N9/3188

    Abstract: There is provided a projector including a projection control unit which controls a projection of a background window and computes location information of at least one projection window projected on the background window, a performance sensing unit which senses an object performance on the background window and the at least one projection window, a communication unit which communicates with at least one other projector different from the projector, and an information control unit which controls an operation of each of the at least one other projector, the operation corresponding to the object performance.

    Abstract translation: 提供了一种投影仪，包括：投影控制单元，其控制背景窗口的投影并计算投影在背景窗口上的至少一个投影窗口的位置信息;感测单元，其感测背景窗口上的物体表现， 至少一个投影窗口，与不同于投影仪的至少一个其他投影仪通信的通信单元，以及控制所述至少一个其他投影仪中的每一个的操作的信息控制单元，其对应于对象性能。

    Flash memory data storage apparatus
    23.
    发明授权
    Flash memory data storage apparatus 有权
    闪存数据存储装置

    公开(公告)号：US07467251B2

    公开(公告)日：2008-12-16

    申请号：US11224662

    申请日：2005-09-12

    Applicant: Min-Gun Park ,  Jin-Wook Lee

    Inventor： Min-Gun Park ,  Jin-Wook Lee

    IPC: G06F13/40 ,  G06F13/38 ,  G06F13/14

    CPC classification number: G06F13/1673 ,  G06F13/1678 ,  G06F13/1689

    Abstract: A flash memory data storage apparatus comprises a flash memory and a flash interface. The flash memory transceives data through a flash bus group. The flash interface includes first through n'th flash input buffers that transfer data to a host bus group in stages in response to first through n'th transfer clock control signals. An i'th flash input buffer provides data through i'th input-buffer bus groups in number of at least Ni. A bus width of each of the i'th input-buffer bus groups is wider than a bus width of each of an (i−l)'th input-buffer bus groups. A period of an i'th transfer clock control signal is longer than a period of an (i−1)'th transfer clock control signal. The Ni is obtained by dividing a bus width of the flash bus group by dividing the bus width of the flash bus group by the bus width of the each of the i'th input-buffer bus groups.

    Abstract translation: 闪存数据存储装置包括闪存和闪存接口。 闪存通过闪存总线组收发数据。 闪存接口包括第一至第n个闪存输入缓冲器，其响应于第一至第n个传输时钟控制信号将数据分阶段地传送到主机总线组。 至少第一个闪存输入缓冲器通过第i个输入缓冲区总线组提供数据。 第i个输入缓冲器总线组中的每一个的总线宽度比第（i-1）个输入缓冲器总线组中的每一个的总线宽度宽。 第i个传送时钟控制信号的周期比第（i-1）个传输时钟控制信号的周期长。 通过将闪存总线组的总线宽度除以每个第i个输入缓冲器总线组的总线宽度来划分闪存总线组的总线宽度来获得Ni。

    CIRCUIT AND METHOD GENERATING PROGRAM VOLTAGE FOR NON-VOLATILE MEMORY DEVICE
    24.
    发明申请
    CIRCUIT AND METHOD GENERATING PROGRAM VOLTAGE FOR NON-VOLATILE MEMORY DEVICE 有权
    电路和方法生成非易失性存储器件的程序电压

    公开(公告)号：US20080084749A1

    公开(公告)日：2008-04-10

    申请号：US11844514

    申请日：2007-08-24

    Applicant: Jin-wook LEE ,  Jin-Yub LEE

    Inventor： Jin-wook LEE ,  Jin-Yub LEE

    IPC: G11C16/00

    CPC classification number: G11C16/12 ,  G11C16/0483

    Abstract: Provided are a circuit and method for generating a program voltage, and a non-volatile memory device using the same. The circuit, which generates a program voltage for programming a memory cell of a semiconductor memory device, includes a program voltage controller and a voltage generating unit. The program voltage controller generates a program voltage control signal according to program/erase operations information. The voltage controller generates a program voltage in response to the program voltage control signal.

    Abstract translation: 提供了用于产生编程电压的电路和方法，以及使用其的非易失性存储器件。 产生用于对半导体存储器件的存储单元进行编程的编程电压的电路包括编程电压控制器和电压产生单元。 程序电压控制器根据编程/擦除操作信息产生编程电压控制信号。 电压控制器响应于编程电压控制信号产生编程电压。

    Method and apparatus for controlling slope of word line voltage in nonvolatile memory device
    27.
    发明申请
    Method and apparatus for controlling slope of word line voltage in nonvolatile memory device 有权
    用于控制非易失性存储器件中字线电压斜率的方法和装置

    公开(公告)号：US20070025155A1

    公开(公告)日：2007-02-01

    申请号：US11354917

    申请日：2006-02-16

    Applicant: Sang-Won Hwang ,  Jin-Wook Lee

    Inventor： Sang-Won Hwang ,  Jin-Wook Lee

    IPC: G11C11/34 ,  G11C16/04

    CPC classification number: G11C16/12 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32

    Abstract: A nonvolatile memory device includes a nonvolatile memory cell array including a plurality of nonvolatile memory cells connected to a plurality of word lines, a word line voltage generator configured to generate first and second sequences of voltage pulses. The device selectively supplies one of the first and second sequences of voltage pulses to a selected one of the word lines to program the nonvolatile memory cells connected to the selected word line. A slope of at least one voltage pulse of the first sequence of voltage pulses is greater than a slope of at least one voltage pulse of the second sequence of voltage pulses. In general, the first sequence is applied to word lines far away from the string select line (SSL), and the second sequence is applied to word lines that are close to the SSL.

    Abstract translation: 非易失性存储器件包括非易失性存储单元阵列，包括连接到多个字线的多个非易失性存储器单元，字线电压发生器，被配置为产生第一和第二电压脉冲序列。 该装置选择性地将第一和第二电压脉冲序列中的一个提供给选定的字线之一，以编程连接到所选字线的非易失存储器单元。 电压脉冲的第一序列的至少一个电压脉冲的斜率大于第二电压脉冲序列的至少一个电压脉冲的斜率。 通常，第一个序列应用于远离字符串选择行（SSL）的字线，第二个序列应用于接近SSL的字线。

    Flash memory device and program verification method thereof
    30.
    发明授权
    Flash memory device and program verification method thereof 有权
    闪存设备及其程序验证方法

    公开(公告)号：US07099196B2

    公开(公告)日：2006-08-29

    申请号：US10712652

    申请日：2003-11-12

    Applicant: Kang-Deog Suh ,  Yeong-Tack Lee ,  Jin-Wook Lee

    Inventor： Kang-Deog Suh ,  Yeong-Tack Lee ,  Jin-Wook Lee

    IPC: G11C16/34

    CPC classification number: G11C16/3454 ,  G11C16/0483 ,  G11C16/30

    Abstract: Disclosed is a flash memory device and a program verification method thereof which can prevent a misjudgment as to whether flash memory cells are programmed or not. The flash memory device includes: a program verification voltage generator for variably generating program verification voltages used to verify whether the flash memory cells are programmed or not and a word line level selector for transferring the program verification voltages to word lines connected to control gates of the flash memory cells. The flash memory cells that are verified as uncertain as to whether the flash memory cells are programmed or not can be completely programmed since the program verification operation is carried out with program verification voltage levels that are changed according to the selective activations of the program verification control signals.

    Abstract translation: 公开了一种闪速存储器件及其程序验证方法，其可以防止对闪存单元是否被编程的错误判断。 闪速存储装置包括：程序验证电压发生器，用于可变地产生用于验证闪存单元是否被编程的程序验证电压;以及字线电平选择器，用于将程序验证电压传送到连接到控制门的字线 闪存单元。 由于程序验证操作是根据程序验证控制的选择性激活而改变的程序验证电压进行的，所以被验证为对闪速存储器单元是否被编程的闪存单元是否可以被完全编程 信号。

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