公开(公告)号：US08344930B2

公开(公告)日：2013-01-01

申请号：US13101127

申请日：2011-05-04

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: H03M1/12

CPC classification number: H03M1/002 ,  H03M1/468

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitor array, a first input capacitor, a first switch module, a second capacitor array, a second input capacitor, a second switch module, a comparator and a SAR controller. The SAR ADC is operated under sampling phases and amplifying phases many times to perform amplifying operations and ADC operations upon input signals to generate digital output data. In addition, because the SAR ADC has both an amplification function and an ADC function, a circuit utilizing the SAR ADC does not require an additional active PGA, and a power consumption of the circuit is decreased.

Abstract translation: 逐次逼近寄存器（SAR）模数转换器（ADC）包括第一电容器阵列，第一输入电容器，第一开关模块，第二电容器阵列，第二输入电容器，第二开关模块，比较器和 一个SAR控制器。 SAR ADC在采样相位和放大阶段多次运行，以对输入信号进行放大操作和ADC操作，以生成数字输出数据。 此外，由于SAR ADC具有放大功能和ADC功能，所以使用SAR ADC的电路不需要额外的有源PGA，电路的功耗也会降低。

公开(公告)号：US20120280846A1

公开(公告)日：2012-11-08

申请号：US13101127

申请日：2011-05-04

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: H03M1/12

CPC classification number: H03M1/002 ,  H03M1/468

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitor array, a first input capacitor, a first switch module, a second capacitor array, a second input capacitor, a second switch module, a comparator and a SAR controller. The SAR ADC is operated under sampling phases and amplifying phases many times to perform amplifying operations and ADC operations upon input signals to generate digital output data. In addition, because the SAR ADC has both an amplification function and an ADC function, a circuit utilizing the SAR ADC does not require an additional active PGA, and a power consumption of the circuit is decreased.

Abstract translation: 逐次逼近寄存器（SAR）模数转换器（ADC）包括第一电容器阵列，第一输入电容器，第一开关模块，第二电容器阵列，第二输入电容器，第二开关模块，比较器和 一个SAR控制器。 SAR ADC在采样相位和放大阶段多次运行，以对输入信号进行放大操作和ADC操作，以生成数字输出数据。 此外，由于SAR ADC具有放大功能和ADC功能，所以使用SAR ADC的电路不需要额外的有源PGA，电路的功耗也会降低。

公开(公告)号：US07924204B2

公开(公告)日：2011-04-12

申请号：US12247186

申请日：2008-10-07

Applicant: Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

Inventor： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC: H03M1/38

CPC classification number: H03M1/1225 ,  H03M1/0695 ,  H03M1/162 ,  H03M1/164 ,  H03M1/40 ,  H03M1/44

Abstract: An analog-to-digital converter (ADC) for pipelined ADCs or cyclic ADCs is disclosed. The ADC includes at least one pair of two stages connected in series, and the two stages have different bits of resolution. An amplifier is shared by the pair of two stages such that the two stages operate in an interleaved manner. Accordingly, this stage-resolution scalable opamp-sharing technique is adaptable for pipelined ADC or cyclic ADC, which substantially reduces power consumption and increases operating speed.

Abstract translation: 公开了一种用于流水线ADC或循环ADC的模数转换器（ADC）。 ADC包括串联连接的至少一对两个级，两级具有不同的分辨率。 放大器由一对两个级共享，使得两个级以交错方式操作。 因此，这种阶段分辨率可扩展的运算放大器共享技术适用于流水线ADC或循环ADC，这大大降低了功耗并提高了运行速度。

公开(公告)号：US20100004747A1

公开(公告)日：2010-01-07

申请号：US12168874

申请日：2008-07-07

Applicant: Jin-Fu LIN

Inventor： Jin-Fu LIN

IPC: A61F2/44 ,  A61B17/70 ,  A61B17/04

CPC classification number: A61B17/7059 ,  A61F2/4465 ,  A61F2002/30281 ,  A61F2002/30433 ,  A61F2002/30507 ,  A61F2002/30576 ,  A61F2002/30594 ,  A61F2002/30604 ,  A61F2002/30777 ,  A61F2002/30785 ,  A61F2002/30848 ,  A61F2002/30884 ,  A61F2002/30899 ,  A61F2002/30904 ,  A61F2220/0025 ,  A61F2220/0041 ,  A61F2230/0086 ,  A61F2310/00023

Abstract: A trans-vertebral and intra-vertebral plate and a rectangular cage with a slot for the plate of spinal fixation device are for neutralizing intervertebral movement for the spinal interbody fusion. The rectangular cage with a vertical or oblique slot is inserted into the intervertebral space from the lateral or anterior side of the spinal column and then the plate is inserted through the slot of the cage and hammered into and buried inside two adjacent vertebral bodies, to achieve three-dimensional intervertebral fixation.

Abstract translation: 椎体和脊椎内椎板和脊柱固定装置板的狭槽的矩形笼，用于中和脊椎椎体内融合的椎间运动。 将具有垂直或斜槽的矩形笼从脊柱的侧面或前侧插入到椎间空间中，然后将板插入笼的狭槽中并敲入并埋在两个相邻的椎体内，以实现 三维椎间固定。

公开(公告)号：US20130044014A1

公开(公告)日：2013-02-21

申请号：US13210229

申请日：2011-08-15

Applicant: Jin-Fu LIN

Inventor： Jin-Fu LIN

IPC: H03M1/12 ,  H03M1/10

CPC classification number: H03M1/1061 ,  H03M1/468 ,  H03M1/804

Abstract: A capacitance mismatch calibrating method for a successive approximation register ADC which includes at least one array of capacitors is provided. The method includes the following steps: firstly, at least two compensating capacitors are configured. A capacitor from the array of capacitors is selected as a capacitor-under-test. Then, the terminal voltages on the terminals of the array of capacitors and on the terminals of the compensating capacitors are determined. A first comparison voltage is outputted based on the determined terminal voltages. Afterwards, a sequence of comparisons is controlled based on the first comparison voltage and a second comparison voltage to output a sequence of corresponding digital bits. Finally, a calibration value is calculated to calibrate the value of a capacitor-under-test according to the digital bits.

Abstract translation: 提供了包括至少一个电容器阵列的逐次逼近寄存器ADC的电容失配校准方法。 该方法包括以下步骤：首先配置至少两个补偿电容器。 选择来自电容器阵列的电容器作为待测电容器。 然后，确定电容器阵列的端子和补偿电容器的端子上的端子电压。 基于确定的端子电压输出第一比较电压。 之后，基于第一比较电压和第二比较电压来控制比较序列，以输出相应的数字位序列。 最后，计算校准值，以根据数字位校准待测电容器的值。

公开(公告)号：US20120268304A1

公开(公告)日：2012-10-25

申请号：US13093649

申请日：2011-04-25

Applicant: JIN-FU LIN ,  CHIA-HSUAN HUANG

Inventor： JIN-FU LIN ,  CHIA-HSUAN HUANG

IPC: H03M1/12 ,  H03K5/00

CPC classification number: H03K5/00 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/45986 ,  H03M1/0604 ,  H03M1/0695 ,  H03M1/442

Abstract: A switched-capacitor circuit which comprises a first sampling capacitor, a second sampling capacitor, an op-amp, a third capacitor, and a fourth capacitor is provided. The first sampling capacitor is disposed to sample an input signal in a sampling phase. The second sampling capacitor is disposed to sample the input signal in the sampling phase. Wherein, in a first amplify phase, the third capacitor stores an offset voltage of the op-amp, the fourth capacitor stores the electric charges which are flowed from the first sampling capacitor and the second sampling capacitor, and in a second amplify phase, the fourth capacitor gives the stored electric charges back to the first sampling capacitor and the second sampling capacitor.

Abstract translation: 提供了包括第一采样电容器，第二采样电容器，运算放大器，第三电容器和第四电容器的开关电容器电路。 第一采样电容器设置成在采样阶段对输入信号进行采样。 第二采样电容器设置成在采样阶段对输入信号进行采样。 其中，在第一放大相位中，第三电容器存储运算放大器的偏移电压，第四电容器存储从第一采样电容器和第二采样电容器流出的电荷，并且在第二放大相位中， 第四电容器将存储的电荷返回到第一采样电容器和第二采样电容器。

公开(公告)号：US20100134173A1

公开(公告)日：2010-06-03

申请号：US12326854

申请日：2008-12-02

Applicant: Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

Inventor： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC: G06G7/184

CPC classification number: H03F3/005 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45654 ,  H03F2200/78 ,  H03F2203/45136 ,  H03F2203/45404 ,  H03F2203/45648

Abstract: A pseudo-differential switched-capacitor circuit using integrator-based common-mode stabilization technique is disclosed. A pseudo-differential switched-capacitor circuit with the differential floating sampling (DFS) technique has a common-mode gain value of one (1). An integrator is electrically coupled to the differential positive/negative outputs of the DFS circuit, and the integrator feeds back integrator output to the DFS circuit by detecting common-mode voltage disturbance at the differential positive output (Vout+) and negative output (Vout−), thereby stabilizing output common-mode level of the differential positive output (Vout+) and negative output (Vout−) at a desirable level.

Abstract translation: 公开了一种使用基于积分器的共模稳定技术的伪差分开关电容器电路。 具有差分浮动采样（DFS）技术的伪差分开关电容电路具有1（1）的共模增益值。 积分器电耦合到DFS电路的差分正/负输出，积分器通过检测差分正输出（Vout +）和负输出（Vout-）的共模电压干扰，将积分器输出反馈到DFS电路。 从而将差分正输出（Vout +）和负输出（Vout-）的输出共模电平稳定在理想水平。