公开(公告)号：US08791558B2

公开(公告)日：2014-07-29

申请号：US12980772

申请日：2010-12-29

Applicant: Jin Ho Bae ,  Ki Young Kim ,  Jong Hyun Nam

Inventor： Jin Ho Bae ,  Ki Young Kim ,  Jong Hyun Nam

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/28 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/17 ,  H01L23/49816 ,  H01L24/09 ,  H01L24/16 ,  H01L24/18 ,  H01L24/20 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/17104 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A stacked semiconductor chip includes a main substrate supporting a semiconductor chip module, wherein the semiconductor module comprises at least two sub semiconductor chip modules each having a sub substrate in which a first semiconductor chip is embedded and at least two second semiconductor chips are stacked on the sub substrate.

Abstract translation: 叠层半导体芯片包括支撑半导体芯片模块的主衬底，其中半导体模块包括至少两个次半导体芯片模块，每个子半导体芯片模块具有嵌入第一半导体芯片的子衬底，并且至少两个第二半导体芯片堆叠在 副底物。

公开(公告)号：US08390128B2

公开(公告)日：2013-03-05

申请号：US12834115

申请日：2010-07-12

Applicant: Jong Hyun Nam ,  Ki Young Kim ,  Jin Ho Bae

Inventor： Jong Hyun Nam ,  Ki Young Kim ,  Jin Ho Bae

IPC: H01L23/48

CPC classification number: H01L23/49833 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48464 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor package includes a semiconductor chip having a first region defined at a center portion of a first surface of the semiconductor chip, and having second and third regions defined on both sides of the first region, respectively. Bonding pads are disposed in the first region and a substrate having a substrate body is disposed in the second region of the semiconductor chip. The substrate includes an extension portion projecting away from the semiconductor chip. The substrate also includes circuit patterns disposed on the substrate body having a first ends placed adjacent to the bonding pads and second ends placed on the extension portion. Connection members electrically connect the first ends of the circuit patterns and the bonding pads.

Abstract translation: 半导体封装包括半导体芯片，其具有限定在半导体芯片的第一表面的中心部分处的第一区域，并且具有分别限定在第一区域两侧的第二和第三区域。 接合焊盘设置在第一区域中，并且具有基板主体的基板设置在半导体芯片的第二区域中。 基板包括远离半导体芯片突出的延伸部分。 衬底还包括布置在衬底主体上的电路图案，其具有邻近接合焊盘放置的第一端和放置在延伸部分上的第二端。 连接构件电连接电路图案的第一端和接合垫。

公开(公告)号：US20110309529A1

公开(公告)日：2011-12-22

申请号：US12980533

申请日：2010-12-29

Applicant: Ki Young KIM ,  Sung Ho HYUN ,  Myung Geon PARK ,  Jin Ho BAE

Inventor： Ki Young KIM ,  Sung Ho HYUN ,  Myung Geon PARK ,  Jin Ho BAE

IPC: H01L27/08 ,  H01L21/66

CPC classification number: H01L24/81 ,  H01L22/14 ,  H01L22/20 ,  H01L24/16 ,  H01L24/48 ,  H01L24/799 ,  H01L24/98 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K3/225 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2203/176 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A module substrate may include a substrate body on which a plurality of chip mounting regions having connection pads are defined. Repair structures may be respectively formed, or placed, in the chip mounting regions. Each repair structure includes conductive layer patterns formed over the connection pads in each chip mounting region, an insulation layer pattern formed over the substrate body in each chip mounting region in such a way as to expose the conductive layer patterns, plastic conductive members formed between the connection pads and the conductive layer patterns, and a plastic insulation member formed between the substrate body and the insulation layer pattern in each chip mounting region.

Abstract translation: 模块基板可以包括其上限定了具有连接焊盘的多个芯片安装区域的基板主体。 修补结构可以分别形成或放置在芯片安装区域中。 每个修复结构包括形成在每个芯片安装区域中的连接焊盘上的导电层图案，在每个芯片安装区域中形成在衬底主体上的绝缘层图案，以暴露导电层图案，形成在导体层图案之间的塑料导电构件 连接焊盘和导电层图案，以及在每个芯片安装区域中形成在基板主体和绝缘层图案之间的塑料绝缘构件。