公开(公告)号：US07821007B2

公开(公告)日：2010-10-26

申请号：US11971191

申请日：2008-01-08

申请人： Jong-Hyun Choi

发明人： Jong-Hyun Choi

IPC分类号： H01L29/76 ,  H01L31/036 ,  H01L31/112

CPC分类号： H01L29/78675 ,  H01L27/1214 ,  H01L29/66757 ,  H01L29/78621 ,  H01L2029/7863

摘要： A thin film transistor, a method of fabricating the same, and a flat panel display device including the same, are provided. According to the method, low resistance regions and high resistance regions can be manufactured through one doping process. The thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate and including source and drain regions, high resistance regions smaller than the source and drain regions, a channel region, and connection regions disposed between the high resistance regions and the channel region; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer above the channel region; an interlayer insulating layer disposed on the gate electrode; and source and drain electrodes disposed on the interlayer insulating layer and electrically connected to the source and drain regions, respectively.

摘要翻译： 提供薄膜晶体管，其制造方法和包括该薄膜晶体管的平板显示装置。 根据该方法，可以通过一个掺杂工艺制造低电阻区域和高电阻区域。 薄膜晶体管包括：基板; 设置在所述基板上并且包括源极和漏极区域的半导体层，小于所述源极和漏极区域的高电阻区域，沟道区域和设置在所述高电阻区域和所述沟道区域之间的连接区域; 设置在所述半导体层上的栅极绝缘层; 设置在所述沟道区域上方的所述栅极绝缘层上的栅电极; 设置在所述栅电极上的层间绝缘层; 以及设置在层间绝缘层上并分别与源极和漏极区电连接的源极和漏极。

公开(公告)号：US20100246300A1

公开(公告)日：2010-09-30

申请号：US12731749

申请日：2010-03-25

申请人： Jong-Hyun Choi ,  Sang-Seok Kang

发明人： Jong-Hyun Choi ,  Sang-Seok Kang

IPC分类号： G11C29/00 ,  G11C7/12

CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C29/025 ,  G11C29/12005 ,  G11C2029/1204

摘要： A semiconductor memory device includes a memory cell array including a first memory cell coupled to a first bit line and a word line, and a second memory cell coupled to a second bit line and the word line and disposed adjacent to the first memory cell. A controller circuit is configured to provide first and second precharge voltages to the first and second bitlines, respectively. The first precharge voltage is provided as a positive power supply voltage and the second precharge voltage is provided as a negative stress voltage during a burn-in test operation. Related methods of operation are also discussed.

摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列包括耦合到第一位线和字线的第一存储器单元，以及耦合到第二位线和字线并且邻近第一存储单元设置的第二存储单元。 控制器电路被配置为分别向第一和第二位线提供第一和第二预充电电压。 第一预充电电压被提供为正电源电压，并且在老化测试操作期间将第二预充电电压设置为负应力电压。 还讨论了相关的操作方法。

公开(公告)号：US20100182223A1

公开(公告)日：2010-07-22

申请号：US12691907

申请日：2010-01-22

申请人： JONG-HYUN CHOI ,  JANG-SOON IM ,  SUNG-HO KIM ,  ILJEONG LEE

发明人： JONG-HYUN CHOI ,  JANG-SOON IM ,  SUNG-HO KIM ,  ILJEONG LEE

IPC分类号： G09G3/30

CPC分类号： G09G3/3233 ,  G09G2300/0417 ,  G09G2300/0842 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/3262 ,  H01L29/7869

摘要： An organic light emitting display device that includes a plurality of signal lines and a plurality of scan lines, a plurality of pixels arranged at intersections of ones of the plurality of signal lines and ones of the plurality of scan lines, a scan driver to supply scan signals to the plurality of scan lines, the scan driver including a first plurality of thin film transistors and a data driver to supply data signals to the plurality of signal lines, the data driver including a second plurality of thin film transistors, wherein each of said plurality of pixels includes a first thin film transistor, a second thin film transistor and an organic light emitting diode, the first transistor being connected to the organic light emitting diode, the first transistor having an active layer made out of an oxide semiconductor, the second transistor, the first plurality of thin film transistors and the second plurality of thin film transistors each having an active layer made out of poly-silicon.

摘要翻译： 一种有机发光显示装置，包括多条信号线和多条扫描线，多条像素排列在多条信号线与多条扫描线中的一条信号线的交点处，扫描驱动器提供扫描 信号到多条扫描线，扫描驱动器包括第一多个薄膜晶体管和数据驱动器，以向多条信号线提供数据信号，数据驱动器包括第二多个薄膜晶体管，其中每个所述薄膜晶体管 多个像素包括第一薄膜晶体管，第二薄膜晶体管和有机发光二极管，第一晶体管连接到有机发光二极管，第一晶体管具有由氧化物半导体制成的有源层，第二晶体管 晶体管，第一多个薄膜晶体管和第二多个薄膜晶体管各自具有由多晶硅制成的有源层。

公开(公告)号：US20090302332A1

公开(公告)日：2009-12-10

申请号：US12475136

申请日：2009-05-29

申请人： Chul-Kyu Kang ,  Do-Hyun Kwon ,  Ju-Won Yoon ,  Jong-Hyun Choi ,  Jun-woo Lee

发明人： Chul-Kyu Kang ,  Do-Hyun Kwon ,  Ju-Won Yoon ,  Jong-Hyun Choi ,  Jun-woo Lee

IPC分类号： H01L33/00 ,  H01L27/06 ,  H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1255 ,  H01L29/4908

摘要： A flat panel display including a semiconductor circuit, and a method of manufacturing the semiconductor circuit are disclosed. In one embodiment, the semiconductor circuit includes i) a substrate, ii) a semiconductor layer and a first capacitor electrode formed on the substrate, the first capacitor electrode being doped to be conductive, iii) an insulating layer covering the semiconductor layer and the first capacitor electrode, iv) a gate electrode disposed on the insulating layer and corresponding to a portion of the semiconductor layer, and v) a second capacitor electrode disposed on the insulating layer and corresponding to the first capacitor electrode, wherein the gate electrode is thicker than the second capacitor electrode.

摘要翻译： 公开了一种包括半导体电路的平板显示器和制造该半导体电路的方法。 在一个实施例中，半导体电路包括i）衬底，ii）形成在衬底上的半导体层和第一电容器电极，第一电容器电极被掺杂为导电，iii）覆盖半导体层和第一 电容器电极，iv）设置在所述绝缘层上并对应于所述半导体层的一部分的栅电极，以及v）设置在所述绝缘层上并对应于所述第一电容器电极的第二电容器电极，其中所述栅电极比 第二电容器电极。

公开(公告)号：US07558128B2

公开(公告)日：2009-07-07

申请号：US11473402

申请日：2006-06-24

申请人： Chang-Ho Shin ,  Jong-Hyun Choi

发明人： Chang-Ho Shin ,  Jong-Hyun Choi

IPC分类号： G11C5/14

CPC分类号： G11C5/145 ,  G11C5/147

摘要： A semiconductor memory device includes a cell array internal voltage generating circuit for generating cell array reference voltage and a cell array internal voltage from a first external power voltage, a peripheral circuit internal voltage generating circuit for generating a peripheral circuit reference voltage and a peripheral circuit internal voltage from the first external power voltage, and a voltage boosting circuit power voltage generating circuit for generating a voltage boosting circuit reference voltage and a voltage boosting circuit power voltage from a second external power voltage.

摘要翻译： 一种半导体存储器件，包括用于产生单元阵列参考电压的单元阵列内部电压产生电路和来自第一外部电源电压的单元阵列内部电压，用于产生外围电路参考电压的外围电路内部电压产生电路和外部电路内部电路的外围电路 来自第一外部电源电压的电压，以及用于从第二外部电源电压产生升压电路参考电压和升压电路电源电压的升压电路电源电压产生电路。

公开(公告)号：US07528644B2

公开(公告)日：2009-05-05

申请号：US11482448

申请日：2006-07-07

申请人： Jong-Hyun Choi ,  Dong-Il Seo

发明人： Jong-Hyun Choi ,  Dong-Il Seo

IPC分类号： H01L35/00

CPC分类号： G01K7/015 ,  G01K2219/00

摘要： A temperature detecting circuit is provided. The temperature detecting circuit includes a reference and detection voltage generator for generating a reference voltage corresponding to a first and a second reference current, and changing first to M-th (M being a natural number) detection currents based on first to M-th temperature detection codes to generate first to M-th detection voltages corresponding to the changed first to M-th detection currents and the second reference current; a temperature detection signal generator for comparing each of the first to M-th detection voltages with the reference voltage to generate first to M-th temperature detection signals; and a temperature detection controller for detecting an operation temperature of a semiconductor device while changing the first to M-th temperature detection codes in response to the first to M-th temperature detection signals from the temperature detection signal generator.

摘要翻译： 提供温度检测电路。 温度检测电路包括用于产生对应于第一和第二参考电流的参考电压的参考和检测电压发生器，并且基于第一至第M温度首先改变为第M（M为自然数）检测电流 检测码，用于产生对应于改变的第一至第M检测电流和第二参考电流的第一至第M检测电压; 温度检测信号发生器，用于将第一至第M检测电压中的每一个与参考电压进行比较，以产生第一至第M温度检测信号; 以及温度检测控制器，用于响应于来自温度检测信号发生器的第一至第M温度检测信号，在改变第一至第M温度检测代码的同时检测半导体器件的工作温度。

公开(公告)号：US20090046531A1

公开(公告)日：2009-02-19

申请号：US12111468

申请日：2008-04-29

申请人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

发明人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

IPC分类号： G11C7/04

CPC分类号： G11C11/402 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40626 ,  G11C2211/4061

摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

摘要翻译： 集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。 内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。 特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

公开(公告)号：US07486576B2

公开(公告)日：2009-02-03

申请号：US11826367

申请日：2007-07-13

申请人： Jong-Hyun Choi ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Young-Hun Seo

发明人： Jong-Hyun Choi ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Young-Hun Seo

IPC分类号： G11C7/00

CPC分类号： G11C11/4078 ,  G11C7/24

摘要： A dynamic random access memory (DRAM) device, including a DRAM core having memory cells for storing data information, and a read protection unit, prevents data stored in the memory cells before power-off, from being read out at power-on.

摘要翻译： 包括具有用于存储数据信息的存储单元的DRAM内核的动态随机存取存储器（DRAM）装置以及在上电期间防止存储在存储单元中的数据在读取电源时被读出的读保护单元。

公开(公告)号：US20080111135A1

公开(公告)日：2008-05-15

申请号：US11935670

申请日：2007-11-06

申请人： Jong-Hyun Choi ,  Kyung-Jin Yoo

发明人： Jong-Hyun Choi ,  Kyung-Jin Yoo

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1277 ,  H01L27/1255 ,  H01L27/1296 ,  H01L27/3244 ,  H01L27/3265 ,  H01L27/3276 ,  H01L51/0021

摘要： An organic light emitting diode display device (OLED display device) having uniform electrical characteristics and a method of manufacturing the same. The OLED display device includes: a substrate; a semiconductor layer disposed on the substrate, and including source and drain regions and a channel region formed using metal induced lateral crystallization (MILC); a gate insulating layer for electrically insulating the semiconductor layer; a gate electrode disposed on the gate insulating layer; an interlayer insulating layer for electrically insulating the gate electrode; a thin film transistor (TFT) including source and drain electrodes that are electrically connected to the source and drain regions of the semiconductor layer; a first electrode for a capacitor disposed on a region of the substrate to be spaced apart from the TFT and formed using a metal induced crystallization (MIC); the gate insulating layer for electrically insulating the first capacitor electrode; a second electrode for the capacitor disposed on the gate insulating layer; a planarization layer disposed on the TFT and the capacitor; a first electrode disposed on the planarization layer; a pixel defining layer disposed on the first electrode; an organic layer disposed on the first electrode and the pixel defining layer, and including at least an emission layer; and a second electrode disposed on the organic layer.

摘要翻译： 一种具有均匀电特性的有机发光二极管显示装置（OLED显示装置）及其制造方法。 OLED显示装置包括：基板; 设置在所述衬底上的半导体层，并且包括源区和漏区以及使用金属诱导横向结晶（MILC）形成的沟道区; 用于使所述半导体层电绝缘的栅极绝缘层; 设置在所述栅极绝缘层上的栅电极; 用于使所述栅电极电绝缘的层间绝缘层; 包括电连接到半导体层的源极和漏极区域的源极和漏极的薄膜晶体管（TFT）; 用于电容器的第一电极，设置在与TFT间隔开并且使用金属诱导结晶（MIC）形成的基板的区域上; 所述栅极绝缘层用于使所述第一电容器电极电绝缘; 用于设置在栅极绝缘层上的电容器的第二电极; 设置在TFT和电容器上的平坦化层; 设置在所述平坦化层上的第一电极; 设置在所述第一电极上的像素限定层; 设置在所述第一电极和所述像素限定层上的有机层，并且至少包括发光层; 以及设置在有机层上的第二电极。

公开(公告)号：US07298655B2

公开(公告)日：2007-11-20

申请号：US11073765

申请日：2005-03-08

申请人： Jong-Hyun Choi ,  Young-Sun Min

发明人： Jong-Hyun Choi ,  Young-Sun Min

IPC分类号： G11C16/04

CPC分类号： G11C11/4091 ,  G11C11/4094 ,  G11C2207/005

摘要： A semiconductor memory includes a memory cell array, a sense amplifier, an isolation device interposed between the sense amplifier and a bit line of the memory cell array, and circuitry for transferring a charge contained in a memory cell of memory cell array to the bit line while the isolation device electrically isolates the bit line from the sense amplifier, and, after the charge is transferred to the bit line, for causing the isolation device to electrically connect the bit line to the sense amplifier.

摘要翻译： 半导体存储器包括存储单元阵列，读出放大器，插入在读出放大器和存储单元阵列的位线之间的隔离装置，以及用于将包含在存储单元阵列的存储单元中的电荷传送到位线 而隔离装置将位线与读出放大器电隔离，并且在电荷被传送到位线之后，用于使隔离装置将位线电连接到读出放大器。