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公开(公告)号：US20100049465A1
公开(公告)日：2010-02-25
申请号：US12526852
申请日：2008-02-21
CPC分类号： H04B17/0085 , H04B17/15 , H04B17/17 , H04B17/19
摘要： An electronic device is disclosed comprising a transceiver stage (140) for communicating signals between the electronic device and a further device; and a baseband processor arrangement (120) implementing a built-in self test arrangement for testing the transceiver channels of the electronic device (100). The built-in self test arrangement further comprises a plurality of records, each record comprising predetermined response deviations to different test signals caused by a parametric fault; and means for selecting those records from the plurality of records for which the predetermined response deviation corresponds to the deviation of the received response. The present invention is based on the realization that a deviation of a response to a test signal from an expected value is dependent on specific parametric faults in specific components in the test signal path and, in addition, on the shape of the test signal. This information is stored in the BIST arrangement and is used to identify a parametric fault, if present, by subjecting the electronic device to a series of test signals.
摘要翻译： 公开了一种电子设备，包括用于在电子设备和另一设备之间传送信号的收发机级（140）; 以及实现用于测试电子设备（100）的收发信道的内置自测试装置的基带处理器装置（120）。 内置自检装置还包括多个记录，每个记录包括由参数故障引起的对不同测试信号的预定响应偏差; 以及用于从预定响应偏差对应于接收到的响应的偏差的多个记录中选择那些记录的装置。 本发明基于这样一种认知，即对来自预期值的测试信号的响应的偏差取决于测试信号路径中的特定组件中的特定参数故障，并且还取决于测试信号的形状。 该信息存储在BIST装置中，并且用于通过使电子设备经受一系列测试信号来识别参数故障（如果存在）。
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公开(公告)号：US07477110B2
公开(公告)日：2009-01-13
申请号：US10588939
申请日：2005-01-27
IPC分类号： G01R31/02
CPC分类号： H03L7/06 , G01R31/2824 , G01R31/30 , G01R31/3161
摘要： According to an example embodiment, there is a testing device for testing a phase locked loop having a power supply input. The testing device comprises a power supply unit for providing a power supply signal VDD having a variation profile to the power supply input of the phase locked loop, wherein a width and height of said variation profile are formed in such a way, that the voltage controlled oscillator is prevented from outputting an oscillating output signal. There is a means for disabling a feedback signal to a phase comparator of the phase locked loop such that said phase locked loop is operated in an open loop mode, and a meter for measuring a measurement signal of the phase locked loop, while said power supply signal is provided to the power supply input.
摘要翻译： 根据示例实施例，存在用于测试具有电源输入的锁相环的测试装置。 测试装置包括电源单元，用于向锁相环的电源输入端提供具有变化曲线的电源信号VDD，其中以这种方式形成所述变化曲线的宽度和高度， 防止振荡器输出振荡输出信号。 存在用于禁用反相信号到相位锁定环路的相位比较器的装置，使得所述锁相环以开环模式操作，以及用于测量锁相环的测量信号的仪表，同时所述电源 信号被提供给电源输入。
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23.发明授权公开(公告)号：US07332953B2
公开(公告)日：2008-02-19
申请号：US10523666
申请日：2003-08-04
IPC分类号： H03K3/01
CPC分类号： H03K19/0027 , H03K2217/0018
摘要： A control unit, for controlling a threshold voltage of a circuit unit having transistor devices, includes a reference circuit and a measuring unit. The measuring unit is configured to measure a threshold voltage of at least one sensing transistor of the circuit unit, and to measure a threshold voltage of at least one reference transistor of the reference circuit. A differential voltage generator is configured to generate a differential voltage from outputs of the measuring unit and a bulk connection of the transistor devices in the circuit unit to which the differential voltage is fed as a biasing voltage.
摘要翻译： 用于控制具有晶体管器件的电路单元的阈值电压的控制单元包括参考电路和测量单元。 测量单元被配置为测量电路单元的至少一个感测晶体管的阈值电压，并且测量参考电路的至少一个参考晶体管的阈值电压。 差分电压发生器被配置为从测量单元的输出和馈送差分电压的电路单元中的晶体管器件的体连接产生差分电压作为偏置电压。
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公开(公告)号：US07200057B2
公开(公告)日：2007-04-03
申请号：US10548340
申请日：2004-03-03
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/5006
摘要： A method and apparatus for testing a static random access memory (SRAM) array for the presence of weak defects. A 0/1 ratio is first written to the memory array (step 100), following which the bit lines BL and BLB are pre-charged and equalized to a threshold detection voltage (step 102). The threshold detection voltage is programmed according to the 0/1 ratio of cells, so as to take into account specific cell criterion and/or characteristics. Next, the word lines associated with all of the cells in the array are enabled substantially simultaneously (step 104), the bit lines are then shorted together (step 106), the word lines are disabled (step 108) and the bit lines are released (step 110). Following these steps, the contents of the SRAM array are read and compared against the original 0/1 ratio (step 112). 10 Any cells whose contents do not match the original 0/1 ratio (i.e. those whose contents have flipped) are marked or otherwise identified as “weak” (step 114).
摘要翻译： 一种用于测试静态随机存取存储器（SRAM）阵列以存在弱缺陷的方法和装置。 首先将0/1比率写入存储器阵列（步骤100），然后将位线BL和BLB预充电并均衡到阈值检测电压（步骤102）。 阈值检测电压根据单元的0/1比率编程，以便考虑特定的单元标准和/或特性。 接下来，与阵列中的所有单元相关联的字线基本上同时被启用（步骤104），然后将位线一起短接（步骤106），字线被禁用（步骤108）并且位线被释放 （步骤110）。 按照这些步骤，读取SRAM阵列的内容并将其与原始的0/1比率进行比较（步骤112）。 内容不符合原始0/1比例（即内容已经翻转的内容）的单元格被标记或以其他方式标识为“弱”（步骤114）。
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公开(公告)号：US08107288B2
公开(公告)日：2012-01-31
申请号：US12666819
申请日：2008-06-25
IPC分类号： G11C16/04
CPC分类号： G11C11/413 , H01L27/0207 , H01L27/105
摘要： A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve reading and writing performance. One of the n-wells and p-wells can be globally biased while the other one of the n-wells and p-wells can be biased by groups, such as blocks, rows or columns. Error reduction and/or correction can be performed by adjusting the well bias.
摘要翻译： 半导体存储器件包括用于构成多个存储单元元件（40）的n阱（22）和p阱（24）。 n阱（22）和p-5孔（24）可以被反向偏置以改善读写性能。 n阱和p阱中的一个可以是全局偏置的，而n阱和p阱中的另一个可以被诸如块，行或列的组偏置。 可以通过调整井偏压来执行误差减小和/或校正。
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公开(公告)号：US20110095803A1
公开(公告)日：2011-04-28
申请号：US11629768
申请日：2005-06-09
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3243 , G06F1/3296 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： The present invention relates to a circuit arrangement and method for controlling power supply in an integrated circuit wherein at least one working parameter of at least one electrically isolated circuit region (10) is monitored, and the conductivity of a variable resistor means is locally controlled so as to individually adjust power supply for each of said at least two electrically isolated circuit regions (10) based on the at least one monitored working parameter. Thereby, a fast and simple control functionality with low area overhead can be provided.
摘要翻译： 本发明涉及一种用于控制集成电路中的电源的电路装置和方法，其中监控至少一个电隔离电路区域（10）的至少一个工作参数，并且可变电阻器装置的电导率被局部控制 用于基于所述至少一个被监视的工作参数单独地调节所述至少两个电隔离电路区域（10）中的每一个的电源。 因此，可以提供具有低面积开销的快速且简单的控制功能。
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公开(公告)号：US20100281245A1
公开(公告)日：2010-11-04
申请号：US11813863
申请日：2006-01-10
申请人： Francesco Pessolano , Rinze L.M.P. Meijer , Jose De Jesus Pineda De Gyvez , Marcus J.M. Heijligers
发明人： Francesco Pessolano , Rinze L.M.P. Meijer , Jose De Jesus Pineda De Gyvez , Marcus J.M. Heijligers
IPC分类号： G06F9/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A digital system 1 comprises receiving means (5) for receiving one or more performance indicators or parameters from software (6) controlling the execution of an application (3). Based on the performance indicators received by the receiving means (5), a tuning circuit (7) is provided for tuning the frequency (f), supply voltage (Vdd) and/or the transistor threshold voltage (Vb) of the digital system (1). In addition, pipeline configuration means (8) are provided for configuring the pipeline of the digital system (1) based on a pipeline depth determined by selecting means (10). The selecting means (10) is configured to select the pipeline depth (Pd) based on the frequency (f), supply voltage (Vdd), transistor threshold voltage (Vb), and according to whether the application requires maximum throughput or minimum latency.
摘要翻译： 数字系统1包括用于从控制应用程序（3）的执行的软件（6）接收一个或多个性能指示符或参数的接收装置（5）。 基于由接收装置（5）接收的性能指标，提供调谐电路（7），用于调谐数字系统的频率（f），电源电压（Vdd）和/或晶体管阈值电压（Vb） 1）。 此外，提供管线配置装置（8），用于基于由选择装置（10）确定的流水线深度来配置数字系统（1）的流水线。 选择装置（10）被配置为基于频率（f），电源电压（Vdd），晶体管阈值电压（Vb）以及根据应用是否需要最大吞吐量或最小等待时间来选择流水线深度（Pd）。
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公开(公告)号：US20100231252A1
公开(公告)日：2010-09-16
申请号：US12160409
申请日：2007-01-05
IPC分类号： G01R31/26
CPC分类号： G01R31/31715 , G01R31/31723 , G01R31/318569 , G01R31/318572
摘要： An integrated circuit (200) comprises a functional block (130) conductively coupled to a supply rail (110) via one or more switches (115). The IC further comprises selection means (220) responsive to a test enable signal for activating the one or more switches (115) in a test mode of the IC and evaluation means such as a comparator (230) having a first input coupled to a reference signal source (215) and having a second input coupled to a node (225) between the one or more switches (115) and the functional block (130) for evaluating the behaviour of the one or more switches (115) based on the reference signal and a signal from the node (225). Thus, the present invention provides a design for testability solution for testing power switches.
摘要翻译： 集成电路（200）包括经由一个或多个开关（115）导电耦合到电源轨（110）的功能块（130）。 IC还包括响应于在IC的测试模式下激活一个或多个开关（115）的测试使能信号的选择装置（220）和诸如比较器（230）的评估装置，该比较器具有耦合到参考的第一输入 信号源（215）并且具有耦合到所述一个或多个开关（115）和所述功能块（130）之间的节点（225）的第二输入，用于基于所述参考来评估所述一个或多个开关（115）的行为 信号和来自节点（225）的信号。 因此，本发明提供了用于测试功率开关的可测试性解决方案的设计。
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公开(公告)号：US20100202192A1
公开(公告)日：2010-08-12
申请号：US12666819
申请日：2008-06-25
IPC分类号： G11C11/412 , G11C5/14
CPC分类号： G11C11/413 , H01L27/0207 , H01L27/105
摘要： A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve reading and writing performance. One of the n-wells and p-wells can be globally biased while the other one of the n-wells and p-wells can be biased by groups, such as blocks, rows or columns. Error reduction and/or correction can be performed by adjusting the well bias.
摘要翻译： 半导体存储器件包括用于构成多个存储单元元件（40）的n阱（22）和p阱（24）。 n阱（22）和p-5孔（24）可以被反向偏置以改善读写性能。 n阱和p阱中的一个可以是全局偏置的，而n阱和p阱中的另一个可以被诸如块，行或列的组偏置。 可以通过调整井偏压来执行误差减小和/或校正。
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公开(公告)号：US20100109676A1
公开(公告)日：2010-05-06
申请号：US12594967
申请日：2008-04-03
IPC分类号： G01R31/02
CPC分类号： G01R31/31813 , G01R31/316
摘要： Test vectors for structural testing of an analog circuit are selected by first selecting an initial set of test input vectors for the analog circuit. A set of faults is selected, comprising faults that each correspond to a respective node in the analog circuit and corresponding fault voltage value for that node. A measure of overlap is computed between probability distributions of test output signal values for the analog circuit in response to the test input vectors in the presence and absence of each of the faults from said set of faults respectively, as a function of estimated statistical spread of component and/or process parameter values in the analog circuit. Test input vectors are selected from the initial set of test input vectors for use in testing on the basis of whether the measure of overlap for at least one if the faults is below a threshold value in response to the selected test input vector under control of the test selection computer.
摘要翻译： 通过首先选择模拟电路的初始测试输入向量集来选择模拟电路结构测试的测试向量。 选择一组故障，其中包括每个对应于模拟电路中的相应节点的故障以及该节点的对应的故障电压值。 在模拟电路的测试输出信号值的概率分布中，根据来自所述故障组的每个故障的存在和不存在的测试输入向量，分别计算重叠的度量，作为估计的统计扩展的函数 模拟电路中的组件和/或过程参数值。 从用于测试的初始测试输入向量组中选择测试输入向量，该测试输入向量基于如果故障低于阈值的至少一个的重叠测量是响应于所选择的测试输入向量在 测试选择电脑。
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