公开(公告)号：US4934774A

公开(公告)日：1990-06-19

申请号：US363006

申请日：1989-06-08

Applicant: Alexander Kalnitsky ,  Joseph P. Ellul ,  Albert R. Boothroyd

Inventor： Alexander Kalnitsky ,  Joseph P. Ellul ,  Albert R. Boothroyd

IPC: G02B6/122 ,  G02B6/134

CPC classification number: G02B6/1347

Abstract: An optical waveguide is made by forming a layer of SiO.sub.2 on a substrate and implanting a region of the SiO.sub.2 layer with Si ions to define a region containing a stoichiometric excess of Si which defines a region having an elevated refractive index surrounded by a region having a lower refractive index. The resulting optical waveguide is stable at the high temperatures required for many semiconductor processing methods, and is useful for optical interconnection in integrated optical and optoelectronic devices.

公开(公告)号：US5614750A

公开(公告)日：1997-03-25

申请号：US496650

申请日：1995-06-29

Applicant: Joseph P. Ellul ,  John M. Boyd

Inventor： Joseph P. Ellul ,  John M. Boyd

IPC: H01L21/8249 ,  H01L27/06 ,  H01L29/417 ,  H01L29/76 ,  H01L27/082 ,  H01L27/102 ,  H01L29/94

CPC classification number: H01L21/743 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/41708

Abstract: A buried layer contact for a integrated circuit structure is provided, with particular application for a contact for a buried collector of a bipolar transistor. The buried layer contact takes the form of a sinker comprising a fully recessed trench isolated structure having dielectric lined sidewalls and filled with conductive material, e.g. doped polysilicon which contacts the buried layer. The trench isolated contact is more compact than a conventional diffused sinker structure, and thus beneficially allows for reduced transistor area. Advantageously, a reduced area sinker reduces the parasitic capacitance and power dissipation. In a practical implementation, the structure provides for an annular collector contact structure to reduce collector resistance.

Abstract translation: 提供了一种用于集成电路结构的掩埋层接触，特别适用于双极晶体管的埋地集电极的接触。 掩埋层接触采取沉降片的形式，其包括完全凹陷的沟槽隔离结构，其具有电介质衬里侧壁并填充有导电材料，例如， 接触埋层的掺杂多晶硅。 沟槽隔离触点比常规扩散沉降片结构更紧凑，因此有利地减少了晶体管面积。 有利的是，减小的面积沉降片减小了寄生电容和功耗。 在实际实施中，该结构提供环形集电极接触结构以减小集电极电阻。

公开(公告)号：US5296258A

公开(公告)日：1994-03-22

申请号：US953373

申请日：1992-09-30

Applicant: Sing P. Tay ,  Joseph P. Ellul

Inventor： Sing P. Tay ,  Joseph P. Ellul

IPC: H01L21/205 ,  C23C16/02 ,  C23C16/32 ,  C23C16/56 ,  H01L21/329 ,  H01L21/331 ,  H01L29/73 ,  H01L29/737 ,  C23C16/00

CPC classification number: H01L29/6609 ,  C23C16/02 ,  C23C16/325 ,  C23C16/56

Abstract: A low temperature CVD method is provided for depositing high quality stoichiometric, poly-crystalline silicon carbide films and for depositing emitter quality, heavily doped silicon carbide films, suitable for application in silicon hetero-junction bipolar transistors. The process is compatible with bipolar-CMOS device processing and comprises pyrolysis of di-tert-butyl silane in an oxygen free ambient, with n-type doping provided by phosphorus source comprising tert-butyl phosphine. Advantageously oxygen is excluded from the reactant gas mixture and the method includes pre-cleaning the susbtrate with nitrogen trifluoride and passivating the silicon carbide film with fluorine species from nitrogen trifluoride.

Abstract translation: 提供低温CVD方法用于沉积高质量化学计量的多晶碳化硅膜并用于沉积适用于硅异质结双极晶体管中的发射体质量的重掺杂碳化硅膜。 该方法与双极CMOS器件处理兼容，并且包括在无氧环境中热解二叔丁基硅烷，由包含叔丁基膦的磷源提供n型掺杂。 有利地，氧气从反应气体混合物中排除，并且该方法包括用三氟化氮预清洗该混合物并用氟化物从三氟化氮钝化碳化硅膜。

公开(公告)号：US5035916A

公开(公告)日：1991-07-30

申请号：US501990

申请日：1990-03-28

Applicant: Alexander Kalnitsky ,  Joseph P. Ellul ,  Albert R. Boothroyd

Inventor： Alexander Kalnitsky ,  Joseph P. Ellul ,  Albert R. Boothroyd

IPC: G02B6/122 ,  G02B6/134

CPC classification number: G02B6/1347

Abstract: An optical waveguide is made by forming a layer of SiO.sub.2 on a substrate and implanting a region of the SiO.sub.2 layer with Si ions to define a region containing a stoichiometric excess of Si which defines a region having an elevated refractive index surrounded by a region having a lower refractive index. The resulting optical waveguide is stable at the high temperatures required for many semiconductor processing methods, and is useful for optical interconnection in integrated optical and optoelectronic devices.

公开(公告)号：US4996081A

公开(公告)日：1991-02-26

申请号：US848609

申请日：1986-04-07

Applicant: Joseph P. Ellul ,  Sing P. Tay

Inventor： Joseph P. Ellul ,  Sing P. Tay

IPC: H01L21/28 ,  H01L21/314 ,  H01L21/321 ,  H01L29/51

CPC classification number: H01L21/28202 ,  H01L21/28273 ,  H01L21/314 ,  H01L21/3211 ,  H01L29/513 ,  H01L29/518

Abstract: In an integrated circuit process a composite dielectric layer is formed on a monocrystalline, polycrystalline or amorphous silicon substrate by thermally growing a first silicon nitride layer from a surface layer of the silicon and then depositing a layer of amorphous or polycrystalline silicon. A second nitride layer is thermally grown from the deposited silicon to form a nitride-silicon-nitride, termed nitsinitride, composite dielectric. At least a top layer of the nitsinitride dielectric can be oxidized to produce an alternative composite dielectric, termed oxidized nitsinitride. Variation of the thickness of the dielectric layers and/or repeating the layering process sequence results in composite dielectrics of different thicknesses and dielectric properties.

Abstract translation: 在集成电路工艺中，通过从硅的表面层热生长第一氮化硅层，然后沉积非晶或多晶硅层，在单晶，多晶或非晶硅衬底上形成复合介质层。 从沉积的硅热生长第二氮化物层以形成氮化硅 - 氮化硅，称为氮化磷，复合电介质。 至少可以将硝基铟电介质的顶层氧化以产生称为氧化的硝基氮化物的替代复合电介质。 电介质层的厚度变化和/或重复层叠工艺顺序导致不同厚度和介电性能的复合电介质。