公开(公告)号：US07397641B2

公开(公告)日：2008-07-08

申请号：US11276411

申请日：2006-02-28

Applicant: Albert M. Chu ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Thomas W. Wyckoff

Inventor： Albert M. Chu ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Thomas W. Wyckoff

IPC: H02H9/00 ,  H02H1/00

CPC classification number: H01L27/0266

Abstract: An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) includes an RC trigger device configured between a pair of power rails, a first control path coupled to the RC trigger device, and a second control path coupled to the RC trigger device. A power clamp is configured between the power rails for discharging current from an ESD event, the power clamp having an input coupled to outputs of the first and second control paths, the power clamp independently controllable by the first and second control paths. The first and second control paths are further configured to prevent the power clamp from reactivating following an initial deactivation of the power clamp.

Abstract translation: 用于保护集成电路免受静电放电（ESD）的装置包括RC触发装置，其配置在耦合到RC触发装置的一对电源轨，第一控制路径和耦合到RC触发装置的第二控制路径之间。 功率钳被配置在用于从ESD事件放电的电源轨之间，功率钳具有耦合到第一和第二控制路径的输出的输入，功率钳由第一和第二控制路径独立地控制。 第一和第二控制路径还被配置为防止在电源钳的初始去激活之后电源钳位被重新激活。

公开(公告)号：US20070053120A1

公开(公告)日：2007-03-08

申请号：US11162198

申请日：2005-08-31

Applicant: Robert Gauthier ,  Junjun Li ,  Souvick Mitra ,  Christopher Putnam

Inventor： Robert Gauthier ,  Junjun Li ,  Souvick Mitra ,  Christopher Putnam

IPC: H02H9/00

CPC classification number: H02H9/046

Abstract: An apparatus for protecting an integrated circuit from an electrostatic discharge (ESD) event includes a multiple stage triggering network configured between a pair of power rails, and a power clamp coupled to the multiple stage triggering network, the power clamp configured to discharge current from the ESD event. The multiple stage triggering network has a first control path and a second control path configured to individually control activation of the power clamp.

Abstract translation: 用于保护集成电路免受静电放电（ESD）事件的装置包括配置在一对电源轨之间的多级触发网络和耦合到多级触发网络的功率钳，该电源钳被配置为从 ESD事件。 多级触发网络具有被配置为单独地控制功率钳的激活的第一控制路径和第二控制路径。

公开(公告)号：US07085113B2

公开(公告)日：2006-08-01

申请号：US10711085

申请日：2004-08-20

Applicant: Robert J. Gauthier, Jr. ,  Junjun Li

Inventor： Robert J. Gauthier, Jr. ,  Junjun Li

IPC: H02H9/00 ,  H02H3/22

CPC classification number: H01L27/0266

Abstract: An ESD protection power clamp for suppressing ESD events. A clamping transistor having power source connections connected across the power supply terminals of an integrated circuit is connected to clamp the voltage during an ESD event. An RC timing circuit defines a time interval where ESD voltage for triggering the FET out of conduction. An inverter circuit connects the RC and timing circuit to the clamping FET. A dynamic feedback transistor is connected in series with one stage of the inverter and the power supply. During an ESD event, the feedback transistor delays the time for disabling the FET transistor, providing increased immunity against mistriggering of the clamping transistor, and forces the circuit to reset following the mistrigger event.

Abstract translation: 用于抑制ESD事件的ESD保护电源钳。 具有连接在集成电路的电源端子上的电源连接的钳位晶体管被连接以在ESD事件期间钳位电压。 RC定时电路定义用于触发FET导通的ESD电压的时间间隔。 逆变器电路将RC和定时电路连接到钳位FET。 动态反馈晶体管与逆变器和电源的一级串联连接。 在ESD事件期间，反馈晶体管延迟了禁止FET晶体管的时间，提供了抵抗钳位晶体管失谐的增强的抗扰性，并迫使电路在雾触发器事件之后复位。

公开(公告)号：US08916426B2

公开(公告)日：2014-12-23

申请号：US13431414

申请日：2012-03-27

Applicant: William F. Clark, Jr. ,  Robert J. Gauthier, Jr. ,  Terence B. Hook ,  Junjun Li ,  Theodorus E. Standaert ,  Thomas A. Wallner

Inventor： William F. Clark, Jr. ,  Robert J. Gauthier, Jr. ,  Terence B. Hook ,  Junjun Li ,  Theodorus E. Standaert ,  Thomas A. Wallner

IPC: H01L21/338 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L27/1211 ,  H01L21/7624 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0262 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785

Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract translation: 无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。 器件区域形成在沟槽中并且与绝缘体上半导体衬底的处理晶片耦合。 器件区域延伸穿过绝缘体上半导体衬底的掩埋绝缘体层朝向绝缘体上半导体衬底的器件层的顶表面。 器件区域由轻掺杂的半导体材料组成。 器件结构还包括形成在器件区域中并限定结的掺杂区域。 器件区域的一部分横向地位于绝缘体上半导体衬底的掺杂区域和掩埋绝缘体层之间。 可以对器件层的另一区域进行构图以形成翅片型场效应晶体管的鳍片。

公开(公告)号：US08891212B2

公开(公告)日：2014-11-18

申请号：US13079946

申请日：2011-04-05

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC: H02H9/04 ,  H03K19/003 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0262 ,  H03K19/00361 ,  Y10T29/49002

Abstract: RC-trigger circuits for a semiconductor controlled rectifier (SCR), methods of providing electrostatic discharge (ESD) protection, and design structures for a RC-trigger circuit. The RC-trigger circuit is coupled to an input/output (I/O) signal pad by an isolation diode and is coupled to a power supply voltage by a power supply diode. Under normal operating conditions, the isolation diode is reverse biased, isolating the RC-trigger circuit from the input/output (I/O) pad, and the power supply diode is forward biased so that the RC-trigger circuit is supplied with power. The isolation diode may become forward biased during ESD events while the chip is unpowered, causing the RC-trigger circuit to trigger an SCR configured protect the signal pad from ESD into a conductive state. The power supply diode may become reverse biased during the ESD event, which isolates the power supply rail from the ESD voltage pulse.

Abstract translation: 用于半导体可控整流器（SCR）的RC触发电路，提供静电放电（ESD）保护的方法以及用于RC触发电路的设计结构。 RC触发电路通过隔离二极管耦合到输入/输出（I / O）信号焊盘，并通过电源二极管耦合到电源电压。 在正常工作条件下，隔离二极管反向偏置，将RC触发电路与输入/输出（I / O）焊盘隔离，电源二极管正向偏置，使RC触发电路供电。 在ESD事件期间，隔离二极管可能会在芯片未上电时产生正向偏置，导致RC触发电路触发SCR配置，从而将信号焊盘从ESD保护到导通状态。 在ESD事件期间，电源二极管可能会反向偏置，从而将电源轨与ESD电压脉冲隔离。

公开(公告)号：US08760827B2

公开(公告)日：2014-06-24

申请号：US12424169

申请日：2009-04-15

Applicant: John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Mujahid Muhammad

Inventor： John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Mujahid Muhammad

IPC: H02H3/22

CPC classification number: H01L27/0274 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit includes a middle junction control circuit that turns off a top NFET of a stacked NFET electrostatic discharge (ESD) protection circuit during an ESD event.

Abstract translation: 公开了用于容错和故障安全设计的强大的ESD保护电路，方法和设计结构。 电路包括在ESD事件期间关闭层叠的NFET静电放电（ESD）保护电路的顶部NFET的中间接点控制电路。

公开(公告)号：US08692290B2

公开(公告)日：2014-04-08

申请号：US13226838

申请日：2011-09-07

Applicant: Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Alain Loiseau

Inventor： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Alain Loiseau

IPC: H01L29/73 ,  H01L21/331 ,  G06F17/50

CPC classification number: H01L29/66363 ,  G06F17/50 ,  H01L27/0262 ,  H01L29/74 ,  H01L29/7436 ,  H02H9/04

Abstract: Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.

Abstract translation: 可控硅整流器的器件结构和设计结构，以及制造可控硅整流器的方法。 器件结构包括设置在包含可控硅整流器的第一和第二p-n结的器件区域的顶表面上的不同材料的第一和第二层。 第一层横向定位在与第一p-n结垂直对准的顶表面上。 第二层横向定位在与第二p-n结垂直对准的器件区域的顶表面上。 包括第二层的材料具有比包含第一层的材料更高的电阻率。

公开(公告)号：US08634174B2

公开(公告)日：2014-01-21

申请号：US13115492

申请日：2011-05-25

Applicant: Michel J. Abou-Khalil ,  James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Yang Yang

Inventor： Michel J. Abou-Khalil ,  James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Yang Yang

IPC: H02H9/00 ,  H02H3/22

CPC classification number: H02H9/046 ,  G06F17/5063 ,  H01L27/0285

Abstract: Protection circuits, design structures, and methods for isolating the gate and gate dielectric of a field-effect transistor from electrostatic discharge (ESD). A protection field-effect transistor is located between a protected field-effect transistor and a voltage rail. Under normal operating conditions, the protection field-effect transistor is saturated so that the protected field-effect transistor is coupled to the voltage rail. The protection field-effect transistor may be driven into a cutoff condition in response to an ESD event while the chip is unpowered, which increases the series resistance of an ESD current path between the gate of the protected field-effect transistor and the voltage rail. The voltage drop across the protection field-effect transistor may reduce the ESD stress on the gate dielectric of the protected field-effect transistor. Alternatively, the gate and source of an existing field-effect transistor are selectively coupled provide ESD isolation to the protected field-effect transistor.

Abstract translation: 用于将场效应晶体管的栅极和栅极电介质与静电放电（ESD）隔离的保护电路，设计结构和方法。 保护场效应晶体管位于受保护的场效应晶体管和电压轨之间。 在正常工作条件下，保护场效应晶体管饱和，使受保护的场效应晶体管耦合到电压轨。 保护场效应晶体管可以在芯片无电源时响应于ESD事件而被驱动成截止状态，这增加了受保护的场效应晶体管的栅极与电压轨之间的ESD电流路径的串联电阻。 保护场效应晶体管两端的电压降可以降低受保护的场效应晶体管的栅极电介质上的ESD应力。 或者，现有的场效应晶体管的栅极和源极被选择性地耦合到提供ESD隔离到受保护的场效应晶体管。

公开(公告)号：US08610217B2

公开(公告)日：2013-12-17

申请号：US12967114

申请日：2010-12-14

Applicant: Robert J. Gauthier, Jr. ,  Mahender Kumar ,  Junjun Li ,  Dustin K. Slisher

Inventor： Robert J. Gauthier, Jr. ,  Mahender Kumar ,  Junjun Li ,  Dustin K. Slisher

IPC: H01L23/62

CPC classification number: H01L23/60 ,  H01L27/0266 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are embodiments of a self-protected electrostatic discharge field effect transistor (SPESDFET). In the SPESDFET embodiments, a resistance region is positioned laterally between two discrete sections of a deep source/drain region: a first section that is adjacent to the channel region and a second section that is contacted. The second section of the deep source/drain region is silicided, but the first section adjacent to the channel region and the resistance region are non-silicided. Additionally, the gate structure can be either silicided or non-silicided. With such a configuration, the disclosed SPESDFET provides robust ESD protection without consuming additional area and without altering the basic FET design (e.g., without increasing the distance between the deep source/drain regions and the channel region). Also disclosed are embodiments of integrated circuit that incorporates the SPESDFET as an input/output (I/O) pad driver and method embodiments for forming the SPESDFET and the integrated circuit.

Abstract translation: 公开了自保护静电放电场效应晶体管（SPESDFET）的实施例。 在SPESDFET实施例中，电阻区域横向定位在深源极/漏极区域的两个离散部分之间：与沟道区域相邻的第一部分和接触的第二部分。 深源极/漏极区域的第二部分被硅化，但是与沟道区域和电阻区域相邻的第一部分是非硅化的。 另外，栅极结构可以是硅化的或非硅化的。 利用这种配置，所公开的SPESDFET提供强大的ESD保护，而不消耗额外的面积，而不改变基本FET设计（例如，不增加深源/漏区和沟道区之间的距离）。 还公开了将SPESDFET作为输入/输出（I / O）焊盘驱动器和用于形成SPESDFET和集成电路的方法实施例的集成电路的实施例。

公开(公告)号：US20130258532A1

公开(公告)日：2013-10-03

申请号：US13431347

申请日：2012-03-27

Applicant: William F. Clark, JR. ,  Robert J. Gauthier, JR. ,  Junjun Li

Inventor： William F. Clark, JR. ,  Robert J. Gauthier, JR. ,  Junjun Li

IPC: H01L27/06 ,  H01L21/20 ,  H01L21/33 ,  G06F17/50 ,  H01L21/8249 ,  H01L29/06 ,  H01L29/73 ,  H02H7/20 ,  H01L21/331

CPC classification number: H01L27/0262 ,  G06F17/5072 ,  H01L21/8249 ,  H01L21/845 ,  H01L27/0255 ,  H01L27/06 ,  H01L27/1211 ,  H01L29/06

Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.