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公开(公告)号：US06608779B1
公开(公告)日：2003-08-19
申请号：US09587495
申请日：2000-06-02
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G06F9/30141 , G06F9/30189
摘要： Embodiments are disclosed that include a low power memory and/or a low power data path. One particular embodiment, for example, includes a technique to reduce power consumption. In one particular embodiment, for example, a grouping of bits, such as a 32-bit word, for example, is stored in inverted form if more than half of the bits have a bit value of logic “1” rather than logic “0.” Likewise, in this embodiment, if more than half of the bits have a bit value of logic “0” rather than logic “1,” then the grouping of bits is not stored in inverted form.
摘要翻译： 公开了包括低功率存储器和/或低功率数据路径的实施例。 例如，一个具体实施例包括减少功耗的技术。 在一个特定实施例中，例如，如果多于一半的比特具有逻辑“1”的比特值而不是逻辑“0”，则比特的诸如32比特字的分组以反向形式被存储 “。 同样，在本实施例中，如果多于一半的比特具有逻辑“0”的比特值而不是逻辑“1”，则比特的分组不以倒置形式存储。
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公开(公告)号：US06512401B2
公开(公告)日：2003-01-28
申请号：US09393134
申请日：1999-09-10
IPC分类号： H03K300
CPC分类号： H03K19/018585
摘要： Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: an output buffer. The output buffer includes semiconductor devices coupled to provide circuit configurations. The output buffer is adapted to couple to separate voltage supply voltage level ports and is further adapted to switch between the circuit configurations. The respective circuit configurations are respectively specifically adapted for interoperating with other integrated circuit chips, the respective threshold voltage levels of the semiconductor devices of different other integrated circuit chips being different.
摘要翻译： 简而言之，根据本发明的一个实施例，集成电路包括：输出缓冲器。 输出缓冲器包括耦合以提供电路配置的半导体器件。 输出缓冲器适于耦合到单独的电压电源电平端口，并且还适于在电路配置之间切换。 相应的电路配置分别专门用于与其他集成电路芯片互操作，不同的其他集成电路芯片的半导体器件的相应阈值电压电平是不同的。
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公开(公告)号：US06368933B1
公开(公告)日：2002-04-09
申请号：US09464023
申请日：1999-12-15
IPC分类号： H01L2120
CPC分类号： H01L23/5286 , H01L27/0203 , H01L27/118 , H01L2924/0002 , Y10T307/582 , H01L2924/00
摘要： An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.
摘要翻译： 集成电路利用电源和接地以外的电压来偏置衬底和阱。 拆除标准电池电路内的电池。 用于偏置衬底的新的抽头电池很好地驻留在标准电池电路之外。 在将分接电池放置在集成电路中之前，指定新电压电源轨的位置。 然后将龙头电池策略性地放置在电源轨附近，使金属连接最小化。 因此，电路密度不会因添加新的电源轨而受到不利影响。 晶体管也放置在抽头单元内，以解决制造过程中的静电放电问题。
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公开(公告)号：US06352914B2
公开(公告)日：2002-03-05
申请号：US09805872
申请日：2001-03-14
申请人： Zane A. Ball , Aviram Gutman , Lawrence T. Clark
发明人： Zane A. Ball , Aviram Gutman , Lawrence T. Clark
IPC分类号： H01L2144
CPC分类号： H01L23/49822 , H01L2224/16225 , H05K1/0219 , H05K1/0298 , H05K2201/09236 , H05K2201/09672
摘要： A multi-layer electronic device package includes first and second outer layers and at least one signal layer disposed between the outer layers. The signal layer includes signal traces and ground traces interleaved with the signal traces. A method of routing signal traces in an electronic device package includes the acts of disposing a plurality of signal traces in at least one substrate layer, and interleaving a plurality of ground traces with the signal traces.
摘要翻译： 多层电子器件封装包括第一和第二外层以及设置在外层之间的至少一个信号层。 信号层包括与信号迹线交错的信号迹线和接地迹线。 在电子器件封装中路由信号迹线的方法包括在至少一个衬底层中设置多个信号迹线以及用信号迹线交织多个接地迹线的动作。
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公开(公告)号：US06282139B1
公开(公告)日：2001-08-28
申请号：US09444538
申请日：1999-11-22
IPC分类号： G11C800
CPC分类号： G11C8/10
摘要： A register file with a plurality of memory cells arranged such that a single word line enable signal path is coupled to word pairs formed from the memory cells, and a logic circuit which is configured to enable separate access of each word of the word pairs.
摘要翻译： 具有多个存储单元的寄存器文件，其被布置成使得单个字线使能信号路径被耦合到由所述存储单元形成的字对;以及逻辑电路，其被配置为使得单词对中的每个单词的单独访问。
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26.发明授权Integrated circuit low leakage power circuitry for use with an advanced CMOS process 有权集成电路低泄漏电源电路，用于先进的CMOS工艺
公开(公告)号：US6166985A
公开(公告)日：2000-12-26
申请号：US302729
申请日：1999-04-30
IPC分类号： G11C11/407 , G11C11/412 , G11C11/413 , G11C11/417 , G11C11/418 , H03K19/00 , H03K19/0948 , G11C8/00
CPC分类号： H03K19/0016 , G11C11/412 , G11C11/417 , G11C11/418
摘要： In one embodiment, the present invention provides a circuit that includes a core circuit and a control circuit coupled to the core circuit. The control circuit reduces a leakage current in the core circuit when the core circuit is in a Sleep mode. The control circuit maintains a logic state of the core circuit when the core circuit is in a Drowsy mode.
摘要翻译： 在一个实施例中，本发明提供一种包括核心电路和耦合到核心电路的控制电路的电路。 当核心电路处于睡眠模式时，控制电路减小了核心电路中的漏电流。 当核心电路处于睡眠模式时，控制电路保持核心电路的逻辑状态。
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27.发明授权
公开(公告)号：US6118482A
公开(公告)日：2000-09-12
申请号：US986499
申请日：1997-12-08
CPC分类号： H04N5/367 , H04N17/002
摘要： CMOS pixel sensors have been of interest as replacements for CCD's in imaging applications. Such devices promise lower power and simpler system level design through fewer power supply voltages and higher functional integration. It is difficult and cost ineffective to utilize images to test active pixel sensors. Here, a method and apparatus for electrical testing of CMOS pixel sensors is described which involves electrically writing a pattern into the CMOS pixel sensors for the detection of adjacent cell shorts or stuck at faults as well as verification of read-channel circuit functionality and performance. The invention provides for an electrical testing of CMOS pixel array that is simple, time efficient and cost effective for use in, for example, production.
摘要翻译： 作为CCD成像应用中的替代品，CMOS像素传感器已经成为关注的焦点。 这样的器件通过更少的电源电压和更高的功能集成来承诺更低的功率和更简单的系统级设计。 利用图像测试有源像素传感器是困难和成本无效的。 这里描述了用于CMOS像素传感器的电测试的方法和装置，其涉及将图案电学写入CMOS像素传感器，用于检测相邻单元短路或卡在故障以及读通道电路功能和性能的验证。 本发明提供了CMOS像素阵列的电气测试，其简单，时间高效并且在例如生产中使用成本有效。
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公开(公告)号：US5859450A
公开(公告)日：1999-01-12
申请号：US941800
申请日：1997-09-30
申请人： Lawrence T. Clark , Mark A. Beiley
发明人： Lawrence T. Clark , Mark A. Beiley
IPC分类号： H01L27/14 , H01L27/146 , H01L31/062 , H01L31/10 , H01L31/113 , H01L27/148
CPC分类号： H01L31/113 , H01L27/1463 , H01L27/14643
摘要： A photodiode is provided. The photodiode includes an insulative region (IR) that permits passage of light therethrough. The photodiode also includes a substrate region of a first conductivity type and a well region of a second conductivity type. The well is formed within the substrate, beneath the IR. The well is demarcated from the substrate by a first surface. The photodiode further includes a heavily doped region (HDR) of the second conductivity type. The HDR is formed within the IR at a first position. The first surface meets the HDR at substantially the first position.
摘要翻译： 提供光电二极管。 光电二极管包括允许光通过其中的绝缘区域（IR）。 光电二极管还包括第一导电类型的衬底区域和第二导电类型的阱区域。 在衬底内形成阱，在IR之下。 孔通过第一表面与基底划分。 光电二极管还包括第二导电类型的重掺杂区域（HDR）。 HDR在第一位置的IR内形成。 第一个表面在大体上的第一个位置与HDR相遇。
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公开(公告)号：US5271040A
公开(公告)日：1993-12-14
申请号：US811092
申请日：1991-12-20
申请人： Lawrence T. Clark
发明人： Lawrence T. Clark
CPC分类号： H03L7/0891 , H03D13/002
摘要： A digital phase detector circuit is designed for particular application with a phase-locked loop voltage controlled oscillator system for synchronizing the MFM synchronization pulses on a floppy disk with the operation of the computer in which the disk is used. A classical Type 4 digital phase detector is employed, to which a bistable latch is added. The latch is set upon coincidence of reference and data pulses applied to the phase detector within a pre-established time interval or window. The output of the phase detector then is utilized only when the output of the latch indicates such coincidence; so that erroneous control signals are not supplied through the loop whenever data pulses fail to occur in adjacent time frames or windows.
摘要翻译： 数字相位检测器电路设计用于具有用于使软盘上的MFM同步脉冲与其中使用盘的计算机的操作同步的锁相环压控振荡器系统的特定应用。 采用经典的4型数字相位检测器，加入双稳态锁存器。 在预先建立的时间间隔或窗口内，基准和数据脉冲一同被施加到相位检测器上设置锁存器。 然后相位检测器的输出仅在锁存器的输出指示这样的重合时才被使用; 使得当相邻时间帧或窗口中的数据脉冲不能发生时，不通过循环提供错误的控制信号。
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公开(公告)号：US20180046580A1
公开(公告)日：2018-02-15
申请号：US15672810
申请日：2017-08-09
申请人： Lawrence T. Clark
发明人： Lawrence T. Clark
IPC分类号： G06F12/0897
摘要： Systems and methods for multi-mode radiation hardened multi-core microprocessors are disclosed. In some embodiments, a triplicated circuit includes a first core logic, a second core logic, a third core logic, and bus arbitration and control circuitry. The triplicated circuit is configurable to operate in both a Triple-Modular Redundant (TMR) mode of operation and a multi-threaded mode of operation. In some embodiments, there is essentially no overhead in soft mode and low overhead (power only) in hard mode. In most applications, it is expected that portions of missions require very hard systems (e.g., landing) where a failure is catastrophic. However, other portions require essentially no hardening (digital signal processor and signal processing activities) but much better throughput. Consequently, there is a huge opportunity to develop computer processors with low overhead in soft mode and unprecedented hardness in hard mode.
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