公开(公告)号：US20240411680A1

公开(公告)日：2024-12-12

申请号：US18330007

申请日：2023-06-06

Applicant: Mellanox Technologies, Ltd.

Inventor： Gil Kremer ,  Roee Moyal ,  Igor Voks ,  Liel Peled ,  Eliel Peretz ,  Ariel Shahar

IPC: G06F12/02

Abstract: Apparatuses, systems, and techniques for dynamic memory allocation using a shared free list. A user tag is received, and a hashed user tag is generated. A first reference to an entry in a second data structure is identified in a first data structure using the hashed user tag. The entry includes multiple user tags. Responsive to determining that the multiple user tags do not include the user tag, a memory address is identified in a third data structure. The memory address is removed from the third data structure. Memory is allocated for a user context associated with the user tag at the memory address. The user tag is added to the second data structure.

公开(公告)号：US12164452B2

公开(公告)日：2024-12-10

申请号：US17874802

申请日：2022-07-27

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dimitrios Syrivelis ,  Ioannis (Giannis) Patronas ,  Paraskevas Bakopoulos ,  Elad Mentovich

IPC: G06F13/28 ,  G06F13/16

Abstract: A high performance mechanism for exporting peripheral services and offloads using Direct Memory Access (DMA) engine is presented. The DMA engine comprises a ring buffer, a DMA memory, and a DMA engine interface operatively coupled to the ring buffer and the DMA memory. The DMA engine interface is configured to retrieve, from the ring buffer, a first DMA request; extract first transfer instructions from the first DMA request; retrieve a first data corresponding to the first DMA request from the DMA memory; and execute the first DMA request using the first data based on at least the first transfer instructions.

公开(公告)号：US20240407096A1

公开(公告)日：2024-12-05

申请号：US18203679

申请日：2023-05-31

Applicant: Mellanox Technologies, Ltd.

Inventor： Ihab KHOURY ,  Tzuf LEVY ,  Ilya MARGOLIN ,  Sharon RECHNITZ ,  Dmitry FLITER ,  David FISCHER ,  Dor DADON

IPC: H05K1/11 ,  B23K1/00 ,  H05K1/14 ,  H05K3/36

Abstract: An electronic sub-assembly, which may include: a ceramic substrate having a top surface and a bottom surface, a plurality of layers of ceramic material disposed between the top surface and the bottom surface of the substrate, and a plurality of conductive structures passing through the substrate between the top surface and the bottom surface of the substrate; and a ball grid array disposed on the bottom surface of the substrate, the ball grid array comprising a plurality of solder balls, wherein at least a portion of the solder balls are connected to at least a portion of the conductive structures.

公开(公告)号：US20240406122A1

公开(公告)日：2024-12-05

申请号：US18203227

申请日：2023-05-30

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Idan Matari ,  Matisyahu Meier Goldmeier ,  George Elias ,  Ofir Klara Altshul ,  Itamar Rabenstein ,  Noam Michaelis ,  Eyal Srebro

IPC: H04L49/101 ,  H04L49/00 ,  H04L49/253

Abstract: An apparatus includes a crossbar circuit that routes one or more packets between one or more ingress domains and one or more egress domains. The crossbar circuit includes sub-crossbar domains. An ingress control circuit associated with the one or more ingress domains may distribute packet data of the one or more packets to the sub-crossbar domains. An egress control circuit of the apparatus receives data bits associated with the packet data from egresses associated with the plurality of sub-crossbar domains. The egress control circuit may reorder or refrain from reordering the data bits based on an attribute associated with the distribution of the packet data.

公开(公告)号：US20240388062A1

公开(公告)日：2024-11-21

申请号：US18198401

申请日：2023-05-17

Applicant: Mellanox Technologies, Ltd.

Inventor： Itshak Kalifa ,  Elad Mentovich ,  Matan Galanty

IPC: H01S5/183

Abstract: High-bandwidth lasers having a balanced intrinsic response and parasitic response are described herein. For example, the present invention may be directed to a laser having an optimized parasitic transfer function and for which the bandwidth of the intrinsic response of the laser is increased by increasing a differential gain of the laser. The laser may balance increased bandwidth of the intrinsic transfer function due to increased cavity length with reduced bandwidth of the parasitic transfer function due to increased active resistance. For example, embodiments of the present invention may be directed to a laser configured to operate at an operating wavelength selected to maximize the bandwidth of the total response of the laser.

公开(公告)号：US20240380636A1

公开(公告)日：2024-11-14

申请号：US18779668

申请日：2024-07-22

Applicant: Mellanox Technologies Ltd.

Inventor： Amit Kazimirsky ,  Nir Sucher

IPC: H04L12/40 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  H04L12/10 ,  H04L43/08

Abstract: Methods, systems, and machine-readable mediums to predict signal conductor traffic and to transition between signal conductor states in accordance with the predictions. In at least one embodiment, a scoring system is used to select a prediction method, which is used to determine when to transition a signal conductor between active and inactive states.

公开(公告)号：US20240373033A1

公开(公告)日：2024-11-07

申请号：US18311489

申请日：2023-05-03

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dror Porat ,  Dotan David Levi ,  Yury Shvartzman ,  Eyal Frishman

IPC: H04N19/147 ,  H04N19/136 ,  H04N19/17

Abstract: Approaches in accordance with various illustrative embodiments provide for the determination and/or optimization the quality of an image or video, such as an image that has been compressed for transmission or storage then decompressed for presentation. Weights can be determined for a set of weight-based quality metrics to produce an overall quality metric that is a weighted combination of these metrics. Because different portions of an image or video frame may have different types of features, an image or video frame can be divided into blocks of pixels, for example, with different weights being assigned to different blocks using quality metrics. Different metrics can be considered as points in a high-dimensional weight space, with each dimension corresponding to a weight of a block. A combination of these points results in an improved quality metric. Compression settings can be updated based in part upon the overall quality metric values.

公开(公告)号：US20240372810A1

公开(公告)日：2024-11-07

申请号：US18312244

申请日：2023-05-04

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Adi Merav Horowitz ,  Omri Kahalon ,  Rabia Loulou ,  Gal Shalom ,  Aviad Yehezkel ,  Liel Yonatan Maman ,  Liran Liss

IPC: H04L47/122 ,  H04L47/19 ,  H04L47/2408 ,  H04L47/6295

Abstract: Multipathing for session-based remote direct memory access (SRDMA) may be used for congestion management. A given SRDMA session group may be associated with multiple SRDMA sessions, each having its own unique 5-tuple. A queue pair (QP) associated with the SRDMA session group may provide a packet for transmission using the SRDMA session group. The SRDMA session group may enable the packet to be transmitted using any of the associated SRDMA sessions. Congestion levels for each of the SRDMA sessions may be monitored and weighted. Therefore, when a packet is received, an SRDMA session may be selected based, at least, on the weight to enable routing of packets to reduce latency and improve overall system efficiency.

公开(公告)号：US20240370592A1

公开(公告)日：2024-11-07

申请号：US18309839

申请日：2023-05-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Alon Singer ,  Zachy Haramaty

IPC: G06F21/78 ,  G06F21/60

Abstract: A device includes multiple registers, multiple hardware-implemented Privilege Level Indicators (PLIs), and one or more circuits. The registers are to store respective values. The PLIs are to specify privilege levels for accessing the respective registers. The one or more circuits are to perform a secure memory dump operation including (i) checking the PLIs of one or more of the registers and (ii) outputting the values of the registers that are permitted for outputting according to the respective PLIs.

公开(公告)号：US20240364633A1

公开(公告)日：2024-10-31

申请号：US18307830

申请日：2023-04-27

Applicant: Mellanox Technologies, Ltd.

Inventor： Michael Weiner ,  Amit Hermony ,  Avi Urman ,  Idan Burstein ,  Yuval Shpigelman

IPC: H04L47/122 ,  H04L43/0852 ,  H04L47/11

CPC classification number: H04L47/122 ,  H04L43/0852 ,  H04L47/11

Abstract: A network device includes one or more ports, processing circuitry, and a memory-network congestion controller. The one or more ports are to connect to a network. The processing circuitry is to run a plurality of processing tasks that access a shared memory, one or more of the processing tasks including communicating one or more packet flows over the network. The memory-network congestion controller is to identify a memory-access congestion, which occurs in accessing the shared memory by one or more of the processing tasks, and to alleviate the memory-access congestion by causing a reduction in a communication rate of at least one of the packet flows.