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    VERTICAL-CAVITY SURFACE-EMITTING LASER (VCSEL) TUNED THROUGH APPLICATION OF MECHANICAL STRESS VIA A PIEZOELECTRIC MATERIAL
    1.
    发明申请
    VERTICAL-CAVITY SURFACE-EMITTING LASER (VCSEL) TUNED THROUGH APPLICATION OF MECHANICAL STRESS VIA A PIEZOELECTRIC MATERIAL 有权

    公开(公告)号：US20210126431A1

    公开(公告)日：2021-04-29

    申请号：US16665435

    申请日：2019-10-28

    申请人： Mellanox Technologies, Ltd.

    发明人： Eran Aharon ,  Itshak Kalifa ,  Elad Mentovich ,  Matan Galanty ,  Isabelle Cestier

    IPC分类号： H01S5/183 ,  H01S5/06 ,  H01L41/113 ,  H01S5/42 ,  H01S5/40

    摘要： A tunable vertical-cavity surface-emitting laser (VCSEL) is provided. The VCSEL includes a VCSEL emission structure, piezoelectric material, and a piezoelectric electrode. The VCSEL emission structure includes a first reflector; a second reflector; and an active cavity material structure disposed between the first and second reflectors. The active cavity material structure includes an active region. The piezoelectric material is mechanically coupled to the VCSEL emission structure such that when the piezoelectric material experiences a mechanical stress, the mechanical stress is transferred to the active cavity material structure of the VCSEL emission structure. The piezoelectric electrode is designed to cause an electric field within the piezoelectric material. The electric field causes the piezoelectric material to experience the mechanical stress, which causes the active cavity material structure to experience the mechanical stress, which causes the emission wavelength of the VCSEL to be modified from a nominal wavelength of the VCSEL.

    HIGH MODULATION SPEED PIN-TYPE PHOTODIODE
    2.
    发明申请
    HIGH MODULATION SPEED PIN-TYPE PHOTODIODE 有权

    公开(公告)号：US20220246781A1

    公开(公告)日：2022-08-04

    申请号：US17249140

    申请日：2021-02-22

    申请人： Mellanox Technologies, Ltd.

    发明人： Yuri Berk ,  Vladimir Iakovlev ,  Tamir Sharkaz ,  Elad Mentovich ,  Matan Galanty ,  Itshak Kalifa ,  Paraskevas Bakopoulos

    IPC分类号： H01L31/105 ,  H01L31/0304

    摘要： Various embodiments of improved PIN-type photodiodes are provided. In an example embodiment, the PIN-type photodiode includes a p-type contact; an n-type contact; a first absorbing layer disposed between the p-type contact and the n-type contact; and a second absorbing layer disposed between the first absorbing layer and the n-type contact. The first absorbing layer is characterized by a first absorption coefficient and the second absorbing layer is characterized by a second absorption coefficient. The second absorption coefficient is greater than the first absorption coefficient. In another example embodiment, the PIN-type photodiode includes a p-type contact; an n-type contact; a first absorbing layer disposed between the p-type contact and the n-type contact; and a non-absorbing accelerating layer disposed between absorbing layers and non-absorbing drift layer and the n-type contact.

    FABRICATION OF LOW-COST LONG WAVELENGTH VCSEL WITH OPTICAL CONFINEMENT CONTROL
    3.
    发明申请
    FABRICATION OF LOW-COST LONG WAVELENGTH VCSEL WITH OPTICAL CONFINEMENT CONTROL 有权

    公开(公告)号：US20220209503A1

    公开(公告)日：2022-06-30

    申请号：US17138623

    申请日：2020-12-30

    申请人： Mellanox Technologies, Ltd.

    发明人： Yuri Berk ,  Vladimir lakovlev ,  Tamir Sharkaz ,  Elad Mentovich ,  Matan Galanty ,  ltshak Kalifa

    IPC分类号： H01S5/183 ,  H01S5/30 ,  H01S5/343 ,  H01S5/125 ,  H01S5/20 ,  H01S5/042

    摘要： Several VCSEL devices for long wavelength applications in wavelength range of 1200-1600 nm are described. These devices include an active region between a semiconductor DBR on a GaAs wafer and a dielectric DBR regrown on the active region. The active region includes multi-quantum layers (MQLs) confined between the active n-InP and p-InAlAs layers and a tunnel junction layer above the MQLs. The semiconductor DBR is fused to the bottom of the active region by a wafer bonding process. The design simplifies integrating the reflectors and the active region stack by having only one wafer bonding followed by regrowth of the other layers including the dielectric DBR. An air gap is fabricated either in an n-InP layer of the active region or in an air gap spacer layer on top of the semiconductor DBR. The air gap enhances optical confinement of the VCSEL. The air gap may also contain a grating.

    VERTICAL-CAVITY SURFACE-EMITTING LASER WITH CHARACTERISTIC WAVELENGTH OF 910 NM
    4.
    发明申请
    VERTICAL-CAVITY SURFACE-EMITTING LASER WITH CHARACTERISTIC WAVELENGTH OF 910 NM 审中-公开

    公开(公告)号：US20200381897A1

    公开(公告)日：2020-12-03

    申请号：US16890149

    申请日：2020-06-02

    申请人： Mellanox Technologies, Ltd.

    发明人： Isabelle Cestier ,  Itshak Kalifa ,  Elad Mentovich ,  Matan Galanty

    IPC分类号： H01S5/183 ,  H01S5/343

    摘要： A vertical-cavity surface-emitting laser (VCSEL) and method of fabrication thereof is provided. The VCSEL includes a mesa structure disposed on a substrate. The mesa structure has a first reflector stack, a second reflector stack, and an active region disposed between the first and second reflector stacks. The active region is configured to cause the VCSEL to emit light having a characteristic wavelength of 910 nanometers. The active region includes alternating layers of quantum wells and barriers, the quantum wells having high indium content (up to 18%). The VCSEL features a first contact layer disposed at least partially on a surface of the mesa structure and configured to serve as an electrical signal layer and a second contact layer disposed at least partially about the mesa structure and configured to serve as an electrical ground.

    Fabrication of low-cost long wavelength VCSEL with optical confinement control
    6.
    发明授权
    Fabrication of low-cost long wavelength VCSEL with optical confinement control 有权

    公开(公告)号：US11611195B2

    公开(公告)日：2023-03-21

    申请号：US17138623

    申请日：2020-12-30

    申请人： Mellanox Technologies, Ltd.

    发明人： Yuri Berk ,  Vladimir Iakovlev ,  Tamir Sharkaz ,  Elad Mentovich ,  Matan Galanty ,  Itshak Kalifa

    IPC分类号： H01S5/00 ,  H01S5/183 ,  H01S5/042 ,  H01S5/343 ,  H01S5/125 ,  H01S5/20 ,  H01S5/30

    摘要： Several VCSEL devices for long wavelength applications in wavelength range of 1200-1600 nm are described. These devices include an active region between a semiconductor DBR on a GaAs wafer and a dielectric DBR regrown on the active region. The active region includes multi-quantum layers (MQLs) confined between the active n-InP and p-InAlAs layers and a tunnel junction layer above the MQLs. The semiconductor DBR is fused to the bottom of the active region by a wafer bonding process. The design simplifies integrating the reflectors and the active region stack by having only one wafer bonding followed by regrowth of the other layers including the dielectric DBR. An air gap is fabricated either in an n-InP layer of the active region or in an air gap spacer layer on top of the semiconductor DBR. The air gap enhances optical confinement of the VCSEL. The air gap may also contain a grating.

    FABRICATING SEMICONDUCTOR DEVICES, SUCH AS VCSELS, WITH AN OXIDE CONFINEMENT LAYER
    7.
    发明申请
    FABRICATING SEMICONDUCTOR DEVICES, SUCH AS VCSELS, WITH AN OXIDE CONFINEMENT LAYER 有权

    公开(公告)号：US20220376476A1

    公开(公告)日：2022-11-24

    申请号：US17303050

    申请日：2021-05-19

    申请人： Mellanox Technologies, Ltd.

    发明人： Yuri Berk ,  Vladimir Iakovlev ,  Anders Larsson ,  Itshak Kalifa ,  Matan Galanty ,  Isabelle Cestier ,  Elad Mentovich

    IPC分类号： H01S5/183 ,  H01S5/343 ,  H01S5/34

    摘要： Methods for forming an at least partially oxidized confinement layer of a semiconductor device and corresponding semiconductor devices are provided. The method comprises forming two or more layers of a semiconductor device on a substrate. The layers include an exposed layer and a to-be-oxidized layer. The to-be-oxidized layer is disposed between the substrate and the exposed layer. The method further comprises etching, using a masking process, a pattern of holes that extend through the exposed layer at least to a first surface of the to-be-oxidized layer. Each hole of the pattern of holes extends in a direction that is transverse to a level plane that is parallel to the first surface of the to-be-oxidized layer. The method further comprises oxidizing the to-be-oxidized layer through the pattern of holes by exposing the two or more layers of the semiconductor device to an oxidizing gas to form a confinement layer.