公开(公告)号：US20080036009A1

公开(公告)日：2008-02-14

申请号：US11502172

申请日：2006-08-10

申请人： Madhukar B. Vora

发明人： Madhukar B. Vora

IPC分类号： H01L31/00

CPC分类号： H01L29/42316 ,  H01L29/1066 ,  H01L29/66901 ,  H01L29/808

摘要： A Junction Field-Effect transistor with no surface contact for the back gate and twice as much transconductance in the channel and with a higher switching speed is achieved by intentionally shorting the channel-well PN junction with the gate region. This is achieved by intentionally etching away field oxide outside the active area at least in the gate region so as to expose the sidewalls of the active area down to the channel-well PN junction or a buried gate which is in electrical contact with the well. Polysilicon is then deposited in the trench and doped heavily and an anneal step is used to drive impurities into the top and sidewalls of the channel region thereby creating a “wrap-around” gate region which reaches down the sidewalls of the channel region to the channel-well PN junction. This causes the bias applied to the gate terminal to also be applied to the well thereby modulating the channel transconductance with the depletion regions around both the gate-channel PN junction and the channel-well PN junction.

摘要翻译： 通过有意短路与栅极区域的沟道阱PN结，实现了对栅极没有表面接触并且在沟道中具有两倍跨导的结场场效应晶体管，并具有较高的开关速度。 这是通过有意地至少在栅极区域中去除有源区域外的场氧化物来实现的，以便将有源区域的侧壁向下暴露于沟道阱PN结或与阱电接触的掩埋栅极。 然后将多晶硅沉积在沟槽中并进行大量掺杂，并且使用退火步骤将杂质驱动到沟道区的顶部和侧壁中，从而形成“环绕”栅极区，其向下延伸到沟道区的侧壁 - PN结。 这导致施加到栅极端子的偏置也被施加到阱，从而调制与栅极 - 沟道PN结和通道阱PN结两端的耗尽区的沟道跨导。

公开(公告)号：US5406133A

公开(公告)日：1995-04-11

申请号：US274817

申请日：1994-07-14

申请人： Madhukar B. Vora ,  Burnell G. West

发明人： Madhukar B. Vora ,  Burnell G. West

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H03K17/00 ,  H03K17/62 ,  H03K19/086 ,  H03K19/173 ,  H03K3/01 ,  H03K17/60

CPC分类号： H03K17/6285 ,  H03K17/6257 ,  H03K19/1737

摘要： A high speed switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed.

摘要翻译： 适用于在高速数据通路中使用电流模式逻辑实现现场可编程门阵列的高速开关技术，以及高速数据通路外的CMOS转向逻辑，以实现高速开关逻辑和实现多路复用器，选择器和交叉开关功能 。 还公开了与高速开关逻辑兼容的高速射极跟随器逻辑，用于电平转换，缓冲和提供更多的电流吸收或源极容量。

公开(公告)号：US5072275A

公开(公告)日：1991-12-10

申请号：US484459

申请日：1990-02-15

申请人： Madhukar B. Vora

发明人： Madhukar B. Vora

IPC分类号： H01L21/8244 ,  H01L21/8249 ,  H01L27/11 ,  H01L29/04 ,  H01L29/08 ,  H01L29/45

CPC分类号： H01L29/0847 ,  H01L21/8249 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/04 ,  H01L29/456 ,  Y10S257/903

摘要： There is disclosed a static RAM cell and MOS device for making the cell along with a process for making the types of devices disclosed. The devices is an MOS device built in an isolated island of epitaxial silicon similar to bipolar device isolation islands, and has single level polysilicon with self-aligned silicide coating for source, drain and gate contacts such that no contact windows need be formed inside the isolation island to make contact with the transistor. The static RAM cell formed using this device uses extensions of the polysilicon contacts outside the isolation islands as shared nodes to implement the conventional cross coupling of various gates to drain and source electrodes of the other transistors in the flip flop. Similarly, extensions of various gate, source and drain contact electrodes are used as shared word lines, and shared Vcc and ground contacts.

摘要翻译： 公开了用于制造该单元的静态RAM单元和MOS器件以及用于使所公开的器件类型的处理。 器件是一种MOS器件，内置隔离孤岛孤岛，与双极器件隔离岛类似，具有单层多晶硅，具有源极，漏极和栅极接触的自对准硅化物涂层，从而不需要在隔离层内形成接触窗口 岛与晶体管接触。 使用该器件形成的静态RAM单元使用隔离岛外部的多晶硅触点的扩展作为共享节点，以实现各种门到触发器中其他晶体管的漏极和源极的常规交叉耦合。 类似地，各种栅极，源极和漏极接触电极的扩展用作共享字线，共享Vcc和接地触点。

公开(公告)号：US4640004A

公开(公告)日：1987-02-03

申请号：US600163

申请日：1984-04-13

申请人： Michael E. Thomas ,  Madhukar B. Vora ,  Ashok K. Kapoor

发明人： Michael E. Thomas ,  Madhukar B. Vora ,  Ashok K. Kapoor

IPC分类号： H01L21/22 ,  H01L21/28 ,  H01L21/285 ,  H01L23/532 ,  H01L29/43 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L21/28518 ,  H01L21/28061 ,  H01L23/53257 ,  H01L29/456 ,  H01L29/4941 ,  H01L2924/0002 ,  Y10S148/034 ,  Y10S438/909

摘要： A method for inhibiting out-diffusion of dopants from polycrystalline or single crystal silicon substrates of high speed semiconductor devices into metal silicide conductive layers disposed on the substrate comprises interposing a refractory metal nitride layer between the doped silicon substrate and the refractory metal silicide conductive layer. Dopant out-diffusion is further retarded, and contact resistance lowered, by adding a thin layer of refractory metal between the refractory metal nitride layer and the silicon substrate.

公开(公告)号：US4622575A

公开(公告)日：1986-11-11

申请号：US647315

申请日：1984-09-04

申请人： Madhukar B. Vora ,  William H. Herndon

发明人： Madhukar B. Vora ,  William H. Herndon

IPC分类号： G11C11/411 ,  H01L27/06 ,  H01L27/102 ,  H01L29/04 ,  H01L27/02 ,  H01L29/70

CPC分类号： H01L27/0688 ,  G11C11/4113 ,  H01L27/1025 ,  Y10S257/914

摘要： A static bipolar random access memory cell includes first and second transistors formed in epitaxial silicon pockets 41 and 42 in a substrate. The collectors 19 and 19' and bases 15 and 15' of the transistors are interconnected with polycrystalline silicon 21 doped to match the conductivity types of the regions contacted. Undesired PN junctions 40 and 40' created thereby are shorted using an overlying layer of a metal silicide 25. In a region overlying the N conductivity type polycrystalline silicon 23 or 23', the metal silicide is removed and a PH junction 37 or 37' created by depositing P conductivity type polycrystalline silicon 35c or 35c'. If desired additional P type polycrystalline silicon 35a and 35b may be deposited across the surface of the epitaxial layer where the base regions of the two transistors are formed to reduce the base series resistance.

摘要翻译： 静态双极性随机存取存储单元包括在衬底中的外延硅袋41和42中形成的第一和第二晶体管。 晶体管的集电极19和19'以及基极15和15'与被掺杂以与所接触的区域的导电类型相匹配的多晶硅21互连。 由此产生的不希望的PN结40和40'使用金属硅化物25的覆盖层而短路。在覆盖N导电型多晶硅23或23'的区域中，去除金属硅化物并产生PH结37或37' 通过沉积P导电型多晶硅35c或35c'。 如果需要，可以在形成两个晶体管的基极区域的外延层的表面上沉积另外的P型多晶硅35a和35b以降低基极串联电阻。

公开(公告)号：US4503598A

公开(公告)日：1985-03-12

申请号：US380170

申请日：1982-05-20

申请人： Madhukar B. Vora ,  Vikram M. Patel

发明人： Madhukar B. Vora ,  Vikram M. Patel

IPC分类号： H01L21/336 ,  H01L23/485 ,  H01L29/10 ,  H01L29/78 ,  H01L21/22 ,  H01L21/467

CPC分类号： H01L29/7802 ,  H01L23/485 ,  H01L29/1095 ,  H01L29/41766 ,  H01L2924/0002

摘要： A power MOSFET semiconductor structure is fabricated using the steps of depositing an epitaxial layer 12 of N conductivity type silicon on an underlying silicon substrate 10 of N conductivity type, forming a plurality of polycrystalline silicon electrodes 18 on the epitaxial layer 12, each electrode 18 being separated from the epitaxial layer 12 by a layer of insulating material 15; introducing P 30 and N 33 conductivity type impurities into the epitaxial layer 12 between the electrodes 18, the P type impurity 30 underlying the N type impurity 33; removing regions of the epitaxial layer 12 to form openings 21 in the epitaxial layer 12 between the electrodes 18, the removed regions 21 extending through the N type region 33 but not through the P type region 30; and depositing electrically conductive material 40 in the opening 23.The resulting semiconductor structure includes an N type substrate 10, an N type epitaxial layer 12, an opening 21 in the epitaxial layer 12 extending downward a selected distance, an upper N type region 33 surrounding the opening 21 and extending to the surface of the epitaxial layer 12, a lower P type region 30 which extends to the surface of the epitaxial layer 12 and everywhere separates the N type region 33 from epitaxial layer 12, an electrode 40 formed in the opening and extending to the upper surface of the epitaxial layer 12, and a second electrode 18 disposed above epitaxial layer 12 and separated from it by insulating material 15.

摘要翻译： 使用以下步骤制造功率MOSFET半导体结构：在N导电类型的下面的硅衬底10上沉积N导电型硅的外延层12，在外延层12上形成多个多晶硅电极18，每个电极18为 通过绝缘材料层15与外延层12分离; 将P 30和N 33导电型杂质引入电极18之间的外延层12，N型杂质33下面的P型杂质30; 去除外延层12的区域，以在电极18之间的外延层12中形成开口21，延伸穿过N型区域33而不通过P型区域30的去除区21; 并且将导电材料40沉积在开口23中。所得的半导体结构包括N型衬底10，N型外延层12，外延层12中向下延伸选定距离的开口21，周围的上N型区域33 开口21并且延伸到外延层12的表面;延伸到外延层12的表面的下部P型区域30，其中N型区域33与外延层12分开，形成在开口中的电极40 并延伸到外延层12的上表面，以及设置在外延层12上方并由绝缘材料15分离的第二电极18。

公开(公告)号：US4435790A

公开(公告)日：1984-03-06

申请号：US474929

申请日：1983-03-14

申请人： Andrew C. Tickle ,  Madhukar B. Vora

发明人： Andrew C. Tickle ,  Madhukar B. Vora

IPC分类号： H01L21/82 ,  H01L27/115 ,  G11C11/40

CPC分类号： H01L21/82 ,  H01L27/115

摘要： A method for encoding binary data into an electrically erasable memory. The memory includes a matrix of memory cells formed as a plurality of rows (X write lines/X sense lines/source lines) and columns (Y sense lines) with each cell including a floating gate field effect PMOS transistor and an NPN bipolar transistor. The method includes applying an erase voltage, e.g. +20 volts, to each of the Y sense lines while maintaining each of the X sense lines at this erase voltage and each of the X write lines at ground and applying the erase voltage to each of the source lines such that each of the PMOS transistors assumes a relatively negative threshold state. The method includes applying a write voltage e.g., +20 volts, to selected X write lines while maintaining unselected X write and selected Y sense lines at ground and unselected Y sense lines at an inhibit voltage e.g., +10 volts, which is less than the write voltage, and maintaining each of the X sense lines at an intermediate voltage e.g., +5 volts, such that the PMOS transistors of memory cells located at the intersections of the selected X write lines and the selected Y sense lines assume a relatively positive threshold state.

摘要翻译： 一种将二进制数据编码为电可擦除存储器的方法。 存储器包括形成为多行（X写入线/ X感测线/源极线）和列（Y感测线）的存储器单元的矩阵，每个单元包括浮置栅极场效应PMOS晶体管和NPN双极晶体管。 该方法包括施加擦除电压，例如， + 20伏，同时将每个X感测线保持在该擦除电压，并将每个X写入线保持在地，并将擦除电压施加到每个源极线，使得每个PMOS晶体管 假定相对负阈值状态。 该方法包括对所选择的X写入线施加例如+ 20伏的写入电压，同时保持未选择的X写入和选择的Y感测线在接地和未选择的Y感测线路处于例如+ 10伏特的抑制电压，其小于 写入电压，并且将每个X检测线保持在例如+ 5V的中间电压，使得位于所选择的X写入线和所选择的Y条线的交点处的存储器单元的PMOS晶体管呈现相对正的阈值 州。

公开(公告)号：US20100019289A1

公开(公告)日：2010-01-28

申请号：US12180098

申请日：2008-07-25

申请人： Ashok K. Kapoor ,  Madhukar B Vora

发明人： Ashok K. Kapoor ,  Madhukar B Vora

IPC分类号： H01L29/80 ,  H01L21/337

CPC分类号： H01L29/8086 ,  H01L29/458 ,  H01L29/66901

摘要： A junction field effect transistor comprises a semiconductor substrate and a well region formed in the substrate. A source region of a first conductivity type is formed in the well region. A drain region of the first conductivity type is formed in the well region and spaced apart from the source region. A channel region of the first conductivity type is located between the source region and the drain region and formed in the well region. A gate region of a second conductivity type is formed in the well region. The transistor further includes first, second, and third connection regions. The first connection region is in ohmic contact with the source region and formed of silicide. The second connection region is in ohmic contact with the drain region and formed of silicide. The third connection region in ohmic contact with the gate region.

摘要翻译： 结型场效应晶体管包括半导体衬底和形成在衬底中的阱区。 在阱区中形成第一导电类型的源极区域。 第一导电类型的漏极区域形成在阱区域中并且与源极区域间隔开。 第一导电类型的沟道区域位于源极区域和漏极区域之间并形成在阱区域中。 在阱区中形成第二导电类型的栅极区域。 晶体管还包括第一，第二和第三连接区域。 第一连接区域与源极区域欧姆接触并由硅化物形成。 第二连接区域与漏区欧姆接触并由硅化物形成。 与栅极区域欧姆接触的第三连接区域。

公开(公告)号：US07557393B2

公开(公告)日：2009-07-07

申请号：US11502172

申请日：2006-08-10

申请人： Madhukar B. Vora

发明人： Madhukar B. Vora

IPC分类号： H01L31/112

CPC分类号： H01L29/42316 ,  H01L29/1066 ,  H01L29/66901 ,  H01L29/808

摘要： A Junction Field-Effect transistor with no surface contact for the back gate and twice as much transconductance in the channel and with a higher switching speed is achieved by intentionally shorting the channel-well PN junction with the gate region. This is achieved by intentionally etching away field oxide outside the active area at least in the gate region so as to expose the sidewalls of the active area down to the channel-well PN junction or a buried gate which is in electrical contact with the well. Polysilicon is then deposited in the trench and doped heavily and an anneal step is used to drive impurities into the top and sidewalls of the channel region thereby creating a “wrap-around” gate region which reaches down the sidewalls of the channel region to the channel-well PN junction. This causes the bias applied to the gate terminal to also be applied to the well thereby modulating the channel transconductance with the depletion regions around both the gate-channel PN junction and the channel-well PN junction.

摘要翻译： 通过有意短路与栅极区域的沟道阱PN结，实现了对栅极没有表面接触并且在沟道中具有两倍跨导的结场场效应晶体管，并具有较高的开关速度。 这是通过有意地至少在栅极区域中去除有源区域外的场氧化物来实现的，以便将有源区域的侧壁向下暴露于沟道阱PN结或与阱电接触的掩埋栅极。 然后将多晶硅沉积在沟槽中并进行大量掺杂，并且使用退火步骤将杂质驱动到沟道区的顶部和侧壁中，从而形成“环绕”栅极区，其向下延伸到沟道区的侧壁 - PN结。 这导致施加到栅极端子的偏置也被施加到阱，从而调制与栅极 - 沟道PN结和通道阱PN结两端的耗尽区的沟道跨导。

公开(公告)号：US20090142889A1

公开(公告)日：2009-06-04

申请号：US12276574

申请日：2008-11-24

申请人： Madhukar B. Vora ,  Ashok Kumar Kapoor

发明人： Madhukar B. Vora ,  Ashok Kumar Kapoor

IPC分类号： H01L21/337

CPC分类号： H01L29/808 ,  H01L29/66901

摘要： A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric layer having a nitride top layer. Metal is deposited on top of said dielectric layer to fill said openings and the metal is polished back to the top of the dielectric layer to achieve thin source, drain and gate contacts. Some embodiments include an anti-leakage poly-silicon layer lining the contact holes and all embodiments where spiking may occur include a barrier metal layer.

摘要翻译： 具有自对准金属源，漏极和栅极接触的JFET结构，具有非常低的电阻率和非常小的特征尺寸。 小的源极，漏极和栅极开口被蚀刻在具有根据期望的源极，栅极和漏极开口尺寸设置的厚度的薄介电层中，所述介电层具有氮化物顶层。 金属沉积在所述电介质层的顶部以填充所述开口并且金属被抛光回到电介质层的顶部以实现薄的源极，漏极和栅极接触。 一些实施例包括衬在接触孔上的防漏多晶硅层，并且可能发生尖峰的所有实施例包括阻挡金属层。